Allows enabling the Clock Recovery System (CRS) for HSI48 to achieve
the expected accuracy for USB transfers. Uses USB SOF packet by default.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
although udiv is represented in clock tree of L series, this is
not really present or controllable from SYSCTL registers. Enable
udiv only if present in dts.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This moves the couple functions that are and will be all over
the various clock operations for all platforms.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Turn MCX series into families.
Reasoning:
1. The MCX SOCs are quite different from each other and having them all
under one family in the HWMv2 hierarchy is fruitless because there
are so many differences that it is confusing to try to introduce
family-level code and configs since they would each only apply to a
subset of the series. There is almost nothing that can be shared
between all of them. Which is why there are comments in the MCX
family files saying not to put anything in them. This is a technical
waste.
2. Therefore, turning all of them into families is almost 0 effort and
makes sense. It will allow these different types of MCX to be
further subdivided into series in the future as the MCX portfolio
expands and such division will be necessary as new SOCs within each
letter family are released.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Do not disable the PLL clock if it sources the XSPI and if the external
flash is executing in Place. After mcuboot reset, the code is executed
on the external flash, through the xspi.
The CONFIG_STM32_APP_IN_EXT_FLASH is set and will avoid re-config
of the PLL which is sourcing the XSPI peripheral. When eXecuting in Place
on this external NOR, it must not disable its own clock source (PLL).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The 'sys' argument in clock_control_renesas_ra_get_rate() is unused and
has been removed to clean up the implementation.
This also aligns with the function's actual behavior and eliminates
misleading validation logic.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Move the call to prepare_regulator_voltage_scale()
before PLL setup in clock_stm32_ll_h7.c.
This ensures the voltage regulator is configured
to the appropriate voltage scale before increasing
the system clock frequency via PLLs.
Without this change, the system configuration
may be out of spec.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Correct PLL input frequency calculation to consider
HSI clock divider in clock_stm32_ll_h7.c file.
For sake of simplicity, use PLLSRC_FREQmacro that
already considers the HSI clock divider when applicable.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Peripheral clocks are currently not being disabled for JTAG reset
condition, which causes driver init failures when debugging the SoC
with JTAG. Fix by disabling all clocks for this reset type.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Fix for compiling i2s drivers on the NXP mimxrt1010_evk board.
For mimxrt1011, the defines kCLOCK_Sai2... are not defined as the sai2
peripheral does not exist. Trying to compile gives error. Fixed by adding
check for device tree node around code that uses the defines. Also added
same for sai1 and sai3. Thanks @lucien-nxp, @ZhaoxiangJin from NXP.
Signed-off-by: Imran Sajjad <imran.sajjad@iconfitness.com>
Enable the RTC-domain and main digital regulators early in clock init,
then load and program the factory/runtime calibrated bias values for
high-power and low-power regulators into the PMU. This ensures the
correct voltage/current settings for stable, low-noise clock operation
in active, modem and sleep modes.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Several reason cause loopback test failed:
a) FlexIO input frequency is not correct, on RT11xx, input freq is 24M,
while max baud rate can reach 1/4 of input freq, so it can only support
6Mbps.
b) Flexio shift register depend on correct timer output to triggger TX
and RX, if timer comparison value is not accurate, RX error happens on
high baud rate. This is the reason why test fails on RT1060.
also fix a error on FlexIO clock ID calculation.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Now that they are handled through their dedicated driver, remove
clock activation for AXISRAM3/4/5/6 (which was useless anyway as
RAMCFG part was missing).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Optimize sckc_get_rate() to be called without configurations in
parameter, the selection of slow clock of the timing domain directly
comes from the register.
Optimize sckc_get_status() with return value "CLOCK_CONTROL_STATUS_ON",
slow clock is always on either driven by the RC oscillator or by the
32.768 kHz crystal oscillator.
Signed-off-by: Tony Han <tony.han@microchip.com>
The STM32MP13 clock control has set and clear registers
for the clocks. So clearing the set register won't have any effect.
Instead, we should write on the clear register.
Signed-off-by: Julien Racki <julien.racki@st.com>
Fix STM32 WBA and H7 clock drivers to release the reference counter
added to access LSE configuration controllers once the clock is
configured. Keeping such an unbalanced access request is no more
needed since SoC functions manage reference counting of access requests.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
By the way, correct stm32_hsem.h header file inclusion that requires
brackets (<>) delimiters, not double quotes, as per convention on header
location.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Add clock bindings for UART/USART (1-9) peripherals in the
`stm32mp2_clock.h`.
Add UART/USART clocks rate reading to the STM32MP2 clock driver.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
There are multi sai instance shared on clock source on
cm33_cpu0, clock driver don't need index parameter, so
modify clock driver to adapt clock driver.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Ensure that the various configuration and conversion tables are marked
as const to save on RAM usage.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Align code with the comment :) There apparently was a copy-paste issue
from the clock_control_on code.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
add missing break statement so that CLOCK_CONTROL_AMBIQ_TYPE_LFXTAL case
is handled correctly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add the stm32mp2 clock driver to the clock_control subsystem. The driver
is a reduced version of the generic stm32 clock driver.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Introduce DeviceTree binding for the STM32MP2 RCC clock controller,
enabling support for STM32MP2-specific clock configuration in Zephyr.
Update Kconfig.stm32 to add a dependency on STM32MP2 configuration,
allowing the use of STM32 LL RCC features when targeting STM32MP2
devices.
Add header for STM32MP2 per peripheral clock definitions.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Currently the config CLOCK_CONTROL_NRF2 is used as a GLOB
style config which includes all "NRF2" drivers and related
configs.
With NRF2, clocks are treated as individidual devices
with individual device drivers. This commit split the
CLOCK_CONTROL_NRF2 config into device specific configs
and ifdefs. With this, drivers are selected individually
based on devicetree state as is common for most devices
drivers, and dependencies like NRFS and specific NRFS
services are selected by the specific driver which nees it.
Checks for CLOCK_CONTROL_NRF2 are updated to check for
existance of the clocks instead.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.
There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When both NRF_CLOCK_HAS_XO_TUNE and NRF_CLOCK_HAS_PLL evaluate to 0,
one break statement can end up not associated with any case and become
dead code. Refactor a bit the related switch to avoid such situation.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
New versions of the Wiseconnect HAL require a clock manager init
function to be called as part of clock configuration.
Without this, the default reference clock isn't configured correctly
for use with peripherals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The application or drivers can request the LFCLK with a given
precision and accuracy.
The driver should select the clock source which has
the lowest power consumption and still satisfies the requested
accuracy and precision.
Before this commit, this was not the case.
Consider the case where the BICR has configured the system
to have LFXO with accuracy of 20 ppm.
The existing code would have ordered the clock options as following:
```
[0] = {LFLPRC, 1000 ppm},
[1] = {LFRC, 500 ppm},
[2] = {SYNTH, 30 ppm},
[3] = {LFXO_PIERCE, 20 ppm},
[4] = {LFXO_PIERCE_HP, 20 ppm}
```
**Example 1**: The user requests the clock with an accuracy of 30 ppm.
The existing code would request the power hungry "SYNTH".
**Example 2**: The user requests a clock with an accuracy of 500 ppm.
The existing code would request the LFRC which consumes more power than
the LFXO.
This commit fixes this issue by ordering the clock sources according
to power consumption.
For the examples above we user request would result in requesting the
20 ppm LFXO.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
