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drivers: clock: conditional compile ulpclk udiv divider

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although udiv is represented in clock tree of L series, this is
not really present or controllable from SYSCTL registers. Enable
udiv only if present in dts.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This commit is contained in:
Parthiban Nallathambi 2025-05-29 20:16:01 +05:30 committed by Anas Nashif
parent 2dc6307628
commit 6bef297052
1 changed files with 2 additions and 0 deletions
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2
drivers/clock_control/clock_control_mspm0.c
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@ -152,7 +152,9 @@ static int clock_mspm0_init(const struct device *dev)
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
DL_SYSCTL_setMCLKDivider(mspm0_mclk_cfg.clk_div);
#if DT_NODE_HAS_PROP(DT_NODELABEL(ulpclk), clk_div)
DL_SYSCTL_setULPCLKDivider(mspm0_ulpclk_cfg.clk_div);
#endif
#if MSPM0_PLL_ENABLED
#if DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll0))