Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce the NRF GPIO Pad Group device driver and binding. The
pad group device represents the GPIO pads (pins), contrary to a
GPIO controller, which is one of the many devices which can be
muxed to pads in the pad group.
The pad group belong to a power domain, which is not neccesarily the
same power domain as devices being muxed to the pads, like GPIO or
UART. If no ACTIVE device is using any of the pads in the pad
group, the pad groups power domain may be SUSPENDED. Before the pad
groups power domain is SUSPENDED, pad config retention must be
enabled to prevent the pads from loosing their state. That's what
this device driver manages. Once retained, the pad configs and
outputs are locked, even when their power domain is SUSPENDED.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Multi-function PMIC AXP2101 now has a fuel gauge driver. Add the
corresponding node to all boards with such a PMIC (also checked their
datasheets and confirmed these actually have a battery correctly
connected to the PMIC).
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The use of timer3 seems to be some legacy leftover from when the
overlay was specific to esp32s3_devkitm originally (commit cf3b2643).
Using timer0 instead.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Incomplete iso IN/OUT is just informative and its occurrence does not
prevent the endpoint from actually transmitting/receiving data. Such
"late" isochronous transfers, which are perfectly fine according to USB
specification, were observed on Windows host with nRF54H20 running
explicit feedback sample operating at High-Speed.
The incorrect handling manifested itself with "ISO RX buffer too small"
error message. The faulty scenario was:
* incompISOIN handler does not find any matching endpoint
* incompISOOUT handler disables endpoint, discards buffer and sets
rearm flag
* next DWC2 interrupt handler iteration after reading GINTSTS
* XferCompl interrupt on iso IN endpoint
* XferCompl interrupt on iso OUT endpoint
- transfer was actually happening to the buffer discarded in
incompISOOUT handler
- XferCompl handler modified the next buffer
* GOUTNakEff interrupt, iso OUT endpoint EPDIS bit is set
* EPDisbld interrupt, rearm flag set
- the buffer modified by XferCompl is used and fails because it is
not large enough
Modify the sequence so it accounts for host actions and the above faulty
scenario no longer causes any problems.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Rearm isochronous endpoints when handling incomplete iso out interrupt
to make it possible to rearm the endpoint in time (before SOF),
especially when operating at High-Speed.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add Seeed Studio as a platform initially unmaintained with rules to match
boards and sheilds.
This should make it easier if someone (ideally from Seeed Studio) would
like to step up to maintain that platform.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Remove build warning when building the posix_arch_console driver with
CONFIG_PRINTK=n and CONFIG_STDOUT_CONSOLE=n.
Fixes: #93790
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The client list is filled from the bonding table at registration
but this should only be done once like the callback registration
Signed-off-by: Yago Fontoura do Rosario <yafo@demant.com>
In current implementation, the UUID 128 is not well supported. The
found issue includes,
Issue 1: No clear byte order of the UUID 128 in local SDP record.
Issue 2: No clear byte order of the UUID 128 of the SDP discover
parameter.
For issue 1,
Add the description to note that if the SDP attribute type is
`BT_SDP_UINT128`, `BT_SDP_INT128`, and `BT_SDP_UUID128`, the byte
order should be little-endian.
And swap the 128bit from little-endian to big-endian when responding
the peer SDP discovery request.
For issue 2,
Add the description to note that if the SDP discovery type is
`Service Search` and `Service Search Attribute`, and UUID is UUID 128,
the passed UUID data of the discovery request parameter should be
represented as the little-endian byte-order sequence.
And swap the 128bit from little-endian to big-endian when packing the
SDP discovery packet.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Add a new shared_heap section. Update the xtensa_soc_mmu_ranges structure
to include a new memory range for the shared heap.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Enable double buffering on isochronous feedback endpoint to avoid
sending ZLP instead of feedback information.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Enable double buffering on data OUT endpoints to allow USB stack to
enqueue next transfer as soon as possible. This is especially useful
when operating at High-Speed where there is significantly less time
between subsequent SOF packets.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Change the macros to have only one plus operator per term. This is
purely stylistic change, no functional changes.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Removed overlay and enabled these nodes in board dts directly as it is
not be valid unless CONFIG_NETWORKING is enabled.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible for netc driver.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added NETC block control device node to handle block control
initialization in netc block driver.
2. Added "nxp,imx-netc" compatible for netc driver.
3. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
As reg property is not used by the driver and there is no proper address
could be assigned to it, so remove it.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add NETC block driver, it could do some block memory region MMIO mapping
and also so dome block initialization, moved some netc related
configuration form board_init() to block driver so that it could be reused
between different platforms, although some configuration is different for
different platform, but put all NETC related code in the same driver to
make it easier to be maintained.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
GIC ITS depends on kernel heap, so move GIC initialize to be behind of
heap which initialization priority is CONFIG_KERNEL_INIT_PRIORITY_OBJECTS
(it is 30 by default).
MU mailbox and SCMI objects depend on GIC, so set their init priority
to be same with GIC, the initialization sequence decided by the dts
dependency although they use the same init priority.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
GIC redistribute and ITS on i.MX 95 is DMA noncoherent, so enable
CONFIG_GIC_V3_RDIST_DMA_NONCOHERENT and CONFIG_GIC_V3_GIC_DMA_NONCOHERENT.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
GIC v3 ITS is initialized in pre-kernel stage in which sleep function
can't work yet, so use busy delay in pre-kernel stage and use sleep
delay in post-kernel stage.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
For RDbase used by its command, When GITS_TYPER.PTA = 1, physicall address
is used, the RDbase field consist of bits[51:16] of the address, so need
to left shift the address by 16 bits. But when GITS_TYPER.PTA = 0, PE
number is used, no need to shit anymore.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
