tests: arm64_gicv3_its: add imx95_evk support

Add imx95_evk support, as hardware limication, it only has 832 LPIs.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

tests/arch/arm64/arm64_gicv3_its/boards/imx95_evk_mimx9596_a55.conf

@@ -0,0 +1,15 @@
+# The GICv3 & ITS drivers allocation needs are:
+# - LPI prop table: global 1x64K aligned on 64K
+# - LPI pend table: for each redistributor/cpu 1x64K aligned on 64K
+# - Devices table: 128x4K aligned on 4K
+# - Interrupt Collections table: 1x4K aligned on 4K
+#
+# This makes 11x64K to permit all allocations to success.
+#
+# Note, will need 64K HEAP_MEM per CPUs added.
+#
+# This doesn't necessarily include the Interrupt Translation Table, which are
+# 256bytes aligned tables, for reference a 32 ITEs table needs 256bytes.
+#
+# To permit allocating 256 ITT tables of 32 ITEs, 13x64K HEAP_MEM is needed
+CONFIG_HEAP_MEM_POOL_SIZE=851968

tests/arch/arm64/arm64_gicv3_its/src/main.c

@@ -19,12 +19,19 @@ static void lpi_irq_handle(const void *parameter)
 	last_lpi_irq_num = i;
 }
 
+#ifdef CONFIG_SOC_MIMX9596_A55
+/* DeviceID is 8bits */
+#define ITS_TEST_DEV(id)        (id & 0xff)
+/* Cover up to 832 LPIs over 26 DevicesIDs and 32 EventIDs per DeviceID */
+#define ITS_TEST_NUM_DEVS       26
+#define ITS_TEST_NUM_ITES       32
+#else
 /* Generate a DeviceID over the whole 16bits */
 #define ITS_TEST_DEV(id)        ((((id + 256) % 16) << 12) | (((id + 256) % 24) << 8) | (id & 0xff))
-
 /* Cover up to 8192 LPIs over 256 DevicesIDs and 32 EventIDs per DeviceID */
 #define ITS_TEST_NUM_DEVS       256
 #define ITS_TEST_NUM_ITES       32
+#endif
 
 /* Do not test all 8192 irqs, iterate with a prime offset to cover most of the possible event_ids */
 #define ITS_TEST_NEXT		13