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drivers: clock_control: mcux_ccm: support QM/QXP's ESAI/AUD_PLL1 clocks

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Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2025-03-18 14:44:27 +02:00 committed by Benjamin Cabé
parent 34d888cbba
commit 1f483b37ea
3 changed files with 65 additions and 3 deletions
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57
drivers/clock_control/clock_control_mcux_ccm.c
View File

@ -20,6 +20,11 @@
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control);
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
#define AUD_PLL_DIV_CLK0_LPCG UINT_TO_POINTER(0x59D20000)
static sc_ipc_t ipc_handle;
#endif
#ifdef CONFIG_SPI_NXP_LPSPI
static const clock_name_t lpspi_clocks[] = {
kCLOCK_Usb1PllPfd1Clk,
@ -81,6 +86,15 @@ static const clock_ip_name_t sai_clocks[] = {
#endif
#endif /* CONFIG_DAI_NXP_SAI */
#ifdef CONFIG_DAI_NXP_ESAI
#if defined(CONFIG_SOC_MIMX8QX6_ADSP) || defined(CONFIG_SOC_MIMX8QM6_ADSP)
static const clock_ip_name_t esai_clocks[] = {
kCLOCK_AUDIO_Esai0,
kCLOCK_AUDIO_Esai1,
};
#endif
#endif /* CONFIG_DAI_NXP_ESAI */
#if defined(CONFIG_I2C_NXP_II2C)
static const clock_ip_name_t i2c_clk_root[] = {
kCLOCK_RootI2c1,
@ -139,6 +153,27 @@ static int mcux_ccm_on(const struct device *dev,
#endif
#endif /* CONFIG_DAI_NXP_SAI */
#ifdef CONFIG_DAI_NXP_ESAI
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
case IMX_CCM_ESAI0_CLK:
case IMX_CCM_ESAI1_CLK:
CLOCK_EnableClock(esai_clocks[instance]);
return 0;
#endif
#endif /* CONFIG_DAI_NXP_ESAI */
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
case IMX_CCM_AUD_PLL_DIV_CLK0:
/* ungate PLL parent */
sc_pm_clock_enable(ipc_handle, SC_R_AUDIO_PLL_0,
SC_PM_CLK_MISC0, true, false);
/* ungate the clock itself */
CLOCK_SetLpcgGate(AUD_PLL_DIV_CLK0_LPCG, true, false, 0xa);
return 0;
#endif
#if defined(CONFIG_ETH_NXP_ENET)
#ifdef CONFIG_SOC_SERIES_IMX8M
#define ENET_CLOCK kCLOCK_Enet1
@ -180,6 +215,27 @@ static int mcux_ccm_off(const struct device *dev,
return 0;
#endif
#endif /* CONFIG_DAI_NXP_SAI */
#ifdef CONFIG_DAI_NXP_ESAI
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
case IMX_CCM_ESAI0_CLK:
case IMX_CCM_ESAI1_CLK:
CLOCK_DisableClock(esai_clocks[instance]);
return 0;
#endif
#endif /* CONFIG_DAI_NXP_ESAI */
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
case IMX_CCM_AUD_PLL_DIV_CLK0:
/* gate the clock itself */
CLOCK_SetLpcgGate(AUD_PLL_DIV_CLK0_LPCG, false, false, 0xa);
/* gate PLL parent */
sc_pm_clock_enable(ipc_handle, SC_R_AUDIO_PLL_0,
SC_PM_CLK_MISC0, false, false);
return 0;
#endif
default:
(void)instance;
return 0;
@ -540,7 +596,6 @@ static DEVICE_API(clock_control, mcux_ccm_driver_api) = {
static int mcux_ccm_init(const struct device *dev)
{
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
sc_ipc_t ipc_handle;
int ret;
ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));

4
dts/xtensa/nxp/nxp_imx8.dtsi
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021, 2024 NXP
* Copyright 2021, 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -156,6 +156,8 @@
reg = <0x59010000 DT_SIZE_K(64)>;
dmas = <&edma0 7 0>, <&edma0 6 0>;
dma-names = "tx", "rx";
clocks = <&ccm IMX_CCM_AUD_PLL_DIV_CLK0 0x0 0x0>,
<&ccm IMX_CCM_ESAI0_CLK 0x0 0x0>;
esai-pin-modes = <ESAI_PIN_HCKR ESAI_PIN_DISCONNECTED>,
<ESAI_PIN_HCKT ESAI_PIN_DISCONNECTED>,
<ESAI_PIN_SDO4_SDI1 ESAI_PIN_DISCONNECTED>,

7
include/zephyr/dt-bindings/clock/imx_ccm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017-2022,2024 NXP
* Copyright 2017-2022,2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -79,4 +79,9 @@
#define IMX_CCM_I2C5_CLK 0x1404UL
#define IMX_CCM_I2C6_CLK 0x1405UL
#define IMX_CCM_ESAI0_CLK 0x1500UL
#define IMX_CCM_ESAI1_CLK 0x1501UL
#define IMX_CCM_AUD_PLL_DIV_CLK0 0x1600UL
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */