soc: nxp: Flatten MCX SOCs

Turn MCX series into families.

Reasoning:
 1. The MCX SOCs are quite different from each other and having them all
    under one family in the HWMv2 hierarchy is fruitless because there
    are so many differences that it is confusing to try to introduce
    family-level code and configs since they would each only apply to a
    subset of the series. There is almost nothing that can be shared
    between all of them. Which is why there are comments in the MCX
    family files saying not to put anything in them. This is a technical
    waste.
 2. Therefore, turning all of them into families is almost 0 effort and
    makes sense. It will allow these different types of MCX to be
    further subdivided into series in the future as the MCX portfolio
    expands and such division will be necessary as new SOCs within each
    letter family are released.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>

drivers/clock_control/clock_control_mcux_syscon.c

@@ -26,7 +26,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 #if defined(CONFIG_COUNTER_NXP_MRT)
 	if ((uint32_t)sub_system == MCUX_MRT_CLK) {
 #if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) ||                          \
-	defined(CONFIG_SOC_SERIES_MCXN)
+	defined(CONFIG_SOC_FAMILY_MCXN)
 		CLOCK_EnableClock(kCLOCK_Mrt);
 #elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
 		CLOCK_EnableClock(kCLOCK_Mrt0);
@@ -46,7 +46,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 
 #if defined(CONFIG_PINCTRL_NXP_PORT)
 	switch ((uint32_t)sub_system) {
-#if defined(CONFIG_SOC_SERIES_MCXA)
+#if defined(CONFIG_SOC_FAMILY_MCXA)
 	case MCUX_PORT0_CLK:
 		CLOCK_EnableClock(kCLOCK_GatePORT0);
 		break;
@@ -80,7 +80,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 	case MCUX_PORT4_CLK:
 		CLOCK_EnableClock(kCLOCK_Port4);
 		break;
-#endif /* defined(CONFIG_SOC_SERIES_MCXA) */
+#endif /* defined(CONFIG_SOC_FAMILY_MCXA) */
 	default:
 		break;
 	}
@@ -94,7 +94,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 
 #if defined(CONFIG_CAN_MCUX_FLEXCAN)
 	switch ((uint32_t)sub_system) {
-#if defined(CONFIG_SOC_SERIES_MCXA)
+#if defined(CONFIG_SOC_FAMILY_MCXA)
 	case MCUX_FLEXCAN0_CLK:
 		CLOCK_EnableClock(kCLOCK_GateFLEXCAN0);
 		break;
@@ -105,7 +105,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 	case MCUX_FLEXCAN1_CLK:
 		CLOCK_EnableClock(kCLOCK_Flexcan1);
 		break;
-#endif /* defined(CONFIG_SOC_SERIES_MCXA) */
+#endif /* defined(CONFIG_SOC_FAMILY_MCXA) */
 	default:
 		break;
 	}
@@ -124,7 +124,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(rtc), okay)
 #if defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX)
 	CLOCK_EnableOsc32K(true);
-#elif CONFIG_SOC_SERIES_MCXN
+#elif CONFIG_SOC_FAMILY_MCXN
 /* 0x0 Clock Select Value Set IRTC to use FRO 16K Clk */
 #if DT_PROP(DT_NODELABEL(rtc), clock_select) == 0x0
 	CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVbat | kCLOCK_Clk16KToMain);
@@ -133,7 +133,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 	CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVbat | kCLOCK_Osc32kToMain);
 #endif /* DT_PROP(DT_NODELABEL(rtc), clock_select) */
 	CLOCK_EnableClock(kCLOCK_Rtc0);
-#endif /* CONFIG_SOC_SERIES_MCXN */
+#endif /* CONFIG_SOC_FAMILY_MCXN */
 #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(rtc), okay) */
 
 	return 0;
@@ -290,7 +290,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 
 #if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
 
-#if defined(CONFIG_SOC_SERIES_MCXN)
+#if defined(CONFIG_SOC_FAMILY_MCXN)
 	case MCUX_USDHC1_CLK:
 		*rate = CLOCK_GetUsdhcClkFreq();
 		break;
@@ -372,9 +372,9 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 
 #if defined(CONFIG_I3C_MCUX)
 	case MCUX_I3C_CLK:
-#if CONFIG_SOC_SERIES_MCXN
+#if CONFIG_SOC_FAMILY_MCXN
 		*rate = CLOCK_GetI3cClkFreq(0);
-#elif CONFIG_SOC_SERIES_MCXA
+#elif CONFIG_SOC_FAMILY_MCXA
 		*rate = CLOCK_GetI3CFClkFreq();
 #else
 		*rate = CLOCK_GetI3cClkFreq();
@@ -382,7 +382,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		break;
 #if (FSL_FEATURE_SOC_I3C_COUNT == 2)
 	case MCUX_I3C2_CLK:
-#if CONFIG_SOC_SERIES_MCXN
+#if CONFIG_SOC_FAMILY_MCXN
 		*rate = CLOCK_GetI3cClkFreq(1);
 #else
 		*rate = CLOCK_GetI3cClkFreq();
@@ -486,7 +486,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 #endif /* CONFIG_ADC_MCUX_LPADC */
 
 #if defined(CONFIG_CAN_MCUX_FLEXCAN)
-#if defined(CONFIG_SOC_SERIES_MCXA)
+#if defined(CONFIG_SOC_FAMILY_MCXA)
 	case MCUX_FLEXCAN0_CLK:
 		*rate = CLOCK_GetFlexcanClkFreq();
 		break;
@@ -497,7 +497,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 	case MCUX_FLEXCAN1_CLK:
 		*rate = CLOCK_GetFlexcanClkFreq(1);
 		break;
-#endif /* defined(CONFIG_SOC_SERIES_MCXA) */
+#endif /* defined(CONFIG_SOC_FAMILY_MCXA) */
 #endif /* defined(CONFIG_CAN_MCUX_FLEXCAN) */
 
 #if defined(CONFIG_MCUX_FLEXIO)
@@ -512,7 +512,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		break;
 #endif /* defined(CONFIG_I2S_MCUX_FLEXCOMM) */
 
-#if (defined(CONFIG_UART_MCUX_LPUART) && CONFIG_SOC_SERIES_MCXA)
+#if (defined(CONFIG_UART_MCUX_LPUART) && CONFIG_SOC_FAMILY_MCXA)
 	case MCUX_LPUART0_CLK:
 		*rate = CLOCK_GetLpuartClkFreq(0);
 		break;
@@ -530,7 +530,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		break;
 #endif /* defined(CONFIG_UART_MCUX_LPUART) */
 
-#if (defined(CONFIG_I2C_MCUX_LPI2C) && CONFIG_SOC_SERIES_MCXA)
+#if (defined(CONFIG_I2C_MCUX_LPI2C) && CONFIG_SOC_FAMILY_MCXA)
 #if (defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT == 1))
 	case MCUX_LPI2C0_CLK:
 		*rate = CLOCK_GetLpi2cClkFreq();
@@ -563,7 +563,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		break;
 #endif /* defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED) */
 
-#if (defined(CONFIG_SPI_NXP_LPSPI) && CONFIG_SOC_SERIES_MCXA)
+#if (defined(CONFIG_SPI_NXP_LPSPI) && CONFIG_SOC_FAMILY_MCXA)
 	case MCUX_LPSPI0_CLK:
 		*rate = CLOCK_GetLpspiClkFreq(0);
 		break;

drivers/flash/soc_flash_mcux.c

@@ -43,7 +43,7 @@ LOG_MODULE_REGISTER(flash_mcux);
 
 #if defined(SOC_HAS_IAP) && !defined(CONFIG_SOC_LPC55S36)
 #include "fsl_iap.h"
-#elif defined(CONFIG_SOC_SERIES_MCXA)
+#elif defined(CONFIG_SOC_FAMILY_MCXA)
 #include "fsl_romapi.h"
 #define FLASH_Erase   FLASH_EraseSector
 #define FLASH_Program FLASH_ProgramPhrase
@@ -118,7 +118,7 @@ static status_t is_area_readable(uint32_t addr, size_t len)
 #endif /* CONFIG_CHECK_BEFORE_READING && ! CONFIG_SOC_SERIES_LPC55XXX */
 
 #define SOC_FLASH_NEED_CLEAR_CACHES 1
-#ifdef CONFIG_SOC_SERIES_MCXW
+#ifdef CONFIG_SOC_FAMILY_MCXW
 static void clear_flash_caches(void)
 {
 	volatile uint32_t *const smscm_ocmdr0 = (volatile uint32_t *)0x40015400;
@@ -128,7 +128,7 @@ static void clear_flash_caches(void)
 	/* this bit clears the code cache */
 	*mcm_cpcr2 |= BIT(0);
 }
-#elif CONFIG_SOC_SERIES_MCXN
+#elif CONFIG_SOC_FAMILY_MCXN
 static void clear_flash_caches(void)
 {
 	volatile uint32_t *const nvm_ctrl = (volatile uint32_t *)0x40000400;
@@ -138,7 +138,7 @@ static void clear_flash_caches(void)
 	/* this bit clears the code cache */
 	*lpcac_ctrl |= BIT(1);
 }
-#elif CONFIG_SOC_SERIES_MCXA
+#elif CONFIG_SOC_FAMILY_MCXA
 static void clear_flash_caches(void)
 {
 	SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC(1U);

drivers/ipm/ipm_mcux.c

@@ -21,7 +21,7 @@
 #define MCUX_IPM_MAX_ID_VAL 0
 
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
-defined(CONFIG_SOC_SERIES_MCXN))
+defined(CONFIG_SOC_FAMILY_MCXN))
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \
 defined(MCXN946_cm33_core0_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
 defined(MCXN546_cm33_core0_SERIES))

drivers/mbox/mbox_nxp_mailbox.c

@@ -22,7 +22,7 @@ LOG_MODULE_REGISTER(nxp_mbox_mailbox);
 #define MAILBOX_MBOX_SIZE    3
 
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) ||                 \
-defined(CONFIG_SOC_SERIES_MCXN))
+defined(CONFIG_SOC_FAMILY_MCXN))
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(MCXN947_cm33_core0_SERIES) ||                  \
 defined(MCXN946_cm33_core0_SERIES) || defined(MCXN547_cm33_core0_SERIES) ||                   \
 defined(MCXN546_cm33_core0_SERIES))

drivers/timer/mcux_os_timer.c

@@ -16,7 +16,7 @@
 #include <zephyr/drivers/counter.h>
 #include <zephyr/pm/pm.h>
 #include "fsl_ostimer.h"
-#if !defined(CONFIG_SOC_SERIES_MCXN) && !defined(CONFIG_SOC_SERIES_MCXA)
+#if !defined(CONFIG_SOC_FAMILY_MCXN) && !defined(CONFIG_SOC_FAMILY_MCXA)
 #include "fsl_power.h"
 #endif
 

drivers/usb/device/usb_dc_mcux.c

@@ -92,7 +92,7 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported");
 #elif defined(CONFIG_SOC_SERIES_IMXRT11XX) || \
 	defined(CONFIG_SOC_SERIES_IMXRT118X) || \
 	defined(CONFIG_SOC_SERIES_IMXRT10XX) || \
-	defined(CONFIG_SOC_SERIES_MCXN)
+	defined(CONFIG_SOC_FAMILY_MCXN)
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1))
 #define CONTROLLER_ID kUSB_ControllerEhci0
 #elif DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2))

drivers/watchdog/wdt_mcux_wwdt.c

@@ -86,12 +86,12 @@ static int mcux_wwdt_install_timeout(const struct device *dev,
 	}
 
 #if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) \
-	|| defined(CONFIG_SOC_SERIES_MCXN) || defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) \
+	|| defined(CONFIG_SOC_FAMILY_MCXN) || defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) \
 	|| defined(CONFIG_SOC_MIMXRT798S_CM33_CPU1)
 	clock_freq = CLOCK_GetWdtClkFreq(0);
 #elif defined(CONFIG_SOC_SERIES_RW6XX)
 	clock_freq = CLOCK_GetWdtClkFreq();
-#elif defined(CONFIG_SOC_SERIES_MCXA)
+#elif defined(CONFIG_SOC_FAMILY_MCXA)
 	clock_freq = CLOCK_GetWwdtClkFreq();
 #else
 	const struct mcux_wwdt_config *config = dev->config;

include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h

@@ -11,7 +11,7 @@
 #include <zephyr/drivers/clock_control.h>
 
 /* Different platforms named the peripheral different in the register definitions */
-#ifdef CONFIG_SOC_SERIES_MCXN
+#ifdef CONFIG_SOC_FAMILY_MCXN
 #undef ENET
 #define ENET_QOS_NAME ENET
 #define ENET_QOS_ALIGNMENT 4

modules/hal_nxp/mcux/Kconfig.mcux

@@ -8,7 +8,7 @@ config HAS_MCUX
 	bool
 	depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \
 		SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW || \
-		SOC_FAMILY_NXP_MCX
+		SOC_FAMILY_MCXN || SOC_FAMILY_MCXA || SOC_FAMILY_MCXW || SOC_FAMILY_MCXC
 
 if	HAS_MCUX
 

modules/hal_nxp/mcux/mcux-sdk-ng/components/components.cmake

@@ -30,14 +30,14 @@ if(CONFIG_NXP_RF_IMU)
     set(CONFIG_MCUX_COMPONENT_driver.gdma ON)
     set(CONFIG_MCUX_COMPONENT_component.wireless_imu_adapter ON)
     set(CONFIG_MCUX_PRJSEG_component.osa_interface.osa_macro_used ON)
-  elseif(CONFIG_SOC_SERIES_MCXW)
+  elseif(CONFIG_SOC_FAMILY_MCXW)
     set(CONFIG_MCUX_COMPONENT_component.lists ON)
     set(CONFIG_MCUX_COMPONENT_component.rpmsg_adapter ON)
     zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
   endif()
 endif()
 
-if(CONFIG_SOC_SERIES_MCXW AND CONFIG_IEEE802154)
+if(CONFIG_SOC_FAMILY_MCXW AND CONFIG_IEEE802154)
   set(CONFIG_MCUX_COMPONENT_driver.spc ON)
   set(CONFIG_MCUX_COMPONENT_component.lists ON)
   set(CONFIG_USE_component_osa_zephyr ON)
@@ -51,7 +51,7 @@ if(CONFIG_USE_component_osa_zephyr)
 endif()
 
 # Component definitions
-if(CONFIG_NXP_RF_IMU AND CONFIG_SOC_SERIES_MCXW)
+if(CONFIG_NXP_RF_IMU AND CONFIG_SOC_FAMILY_MCXW)
   zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
 endif()
 

modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

@@ -147,7 +147,7 @@ set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC          CONFIG_MCUX_COMPONENT_driver
 set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT10XX    CONFIG_MCUX_COMPONENT_driver.ocotp)
 set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT11XX    CONFIG_MCUX_COMPONENT_driver.ocotp)
 set_variable_ifdef(CONFIG_SOC_FAMILY_KINETIS      CONFIG_MCUX_COMPONENT_driver.port)
-set_variable_ifdef(CONFIG_SOC_SERIES_MCXW         CONFIG_MCUX_COMPONENT_driver.ccm32k)
+set_variable_ifdef(CONFIG_SOC_FAMILY_MCXW         CONFIG_MCUX_COMPONENT_driver.ccm32k)
 set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT5XX     CONFIG_MCUX_COMPONENT_driver.iap3)
 
 if(CONFIG_ETH_NXP_IMX_NETC)
@@ -162,11 +162,11 @@ if(CONFIG_ETH_NXP_IMX_NETC)
   set_variable_ifdef(CONFIG_SOC_MIMX9596_M7 CONFIG_MCUX_COMPONENT_driver.irqsteer)
 endif()
 
-if(CONFIG_SOC_SERIES_MCXN OR CONFIG_SOC_SERIES_MCXA)
+if(CONFIG_SOC_FAMILY_MCXN OR CONFIG_SOC_FAMILY_MCXA)
   set(CONFIG_MCUX_COMPONENT_driver.mcx_spc ON)
 endif()
 
-if(CONFIG_BT_NXP AND CONFIG_SOC_SERIES_MCXW OR CONFIG_IEEE802154_MCXW)
+if(CONFIG_BT_NXP AND CONFIG_SOC_FAMILY_MCXW OR CONFIG_IEEE802154_MCXW)
   set(CONFIG_MCUX_COMPONENT_driver.spc ON)
 endif()
 
@@ -188,7 +188,7 @@ else()
   set_variable_ifdef(CONFIG_MBOX_NXP_IMX_MU	CONFIG_MCUX_COMPONENT_driver.mu)
 endif()
 
-if(CONFIG_SOC_FAMILY_KINETIS OR CONFIG_SOC_SERIES_MCXC)
+if(CONFIG_SOC_FAMILY_KINETIS OR CONFIG_SOC_FAMILY_MCXC)
   set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.flash)
 endif()
 
@@ -198,7 +198,7 @@ if(CONFIG_SOC_MK82F25615 OR CONFIG_SOC_MK64F12 OR CONFIG_SOC_MK66F18 OR
   set(CONFIG_MCUX_COMPONENT_driver.sysmpu ON)
 endif()
 
-if(CONFIG_SOC_SERIES_MCXW OR CONFIG_SOC_MCXN947 OR CONFIG_SOC_MCXN547)
+if(CONFIG_SOC_FAMILY_MCXW OR CONFIG_SOC_MCXN947 OR CONFIG_SOC_MCXN547)
   set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.flash_k4)
 endif()
 
@@ -259,11 +259,11 @@ if(CONFIG_SOC_SERIES_IMXRT118X)
   set_variable_ifdef(CONFIG_WDT_MCUX_RTWDOG	CONFIG_MCUX_COMPONENT_driver.src_3)
 endif()
 
-if(CONFIG_SOC_SERIES_MCXA)
+if(CONFIG_SOC_FAMILY_MCXA)
   set(CONFIG_MCUX_COMPONENT_driver.romapi ON)
 endif()
 
-if(CONFIG_SOC_SERIES_MCXN AND (NOT CONFIG_SOC_MCXN947) AND (NOT CONFIG_SOC_MCXN547))
+if(CONFIG_SOC_FAMILY_MCXN AND (NOT CONFIG_SOC_MCXN947) AND (NOT CONFIG_SOC_MCXN547))
   set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.romapi_flashiap)
 endif()
 
@@ -271,7 +271,7 @@ if(CONFIG_SOC_FAMILY_NXP_IMXRT)
   set_variable_ifdef(CONFIG_ETH_NXP_ENET CONFIG_MCUX_COMPONENT_driver.ocotp)
 endif()
 
-set_variable_ifdef(CONFIG_SOC_SERIES_MCXW CONFIG_MCUX_COMPONENT_driver.elemu)
+set_variable_ifdef(CONFIG_SOC_FAMILY_MCXW CONFIG_MCUX_COMPONENT_driver.elemu)
 
 #specific operation to shared drivers
 if((DEFINED CONFIG_FLASH_MCUX_FLEXSPI_XIP) AND (DEFINED CONFIG_FLASH))

soc/nxp/mcx/CMakeLists.txt

@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-add_subdirectory(${SOC_SERIES})
+add_subdirectory(${SOC_FAMILY})

soc/nxp/mcx/Kconfig

@@ -1,15 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-# Do NOT select anything from the MCX family kconfig,
-# and do not make it a dependency of anything else.
-# If there is some similarity between series,
-# use if SERIES_A || SERIES_B or something of that
-# effect rather than the family config.
-# This is because MCX series is expected to be very diverse.
-
-if SOC_FAMILY_NXP_MCX
-
 rsource "*/Kconfig"
-
-endif # SOC_FAMILY_NXP_MCX

soc/nxp/mcx/Kconfig.defconfig

@@ -1,15 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
-#
-# Do NOT select anything from the MCX family kconfig,
-# and do not make it a dependency of anything else.
-# If there is some similarity between series,
-# use if SERIES_A || SERIES_B or something of that
-# effect rather than the family config.
-# This is because MCX series is expected to be very diverse.
-
-if SOC_FAMILY_NXP_MCX
 
 rsource "*/Kconfig.defconfig"
-
-endif # SOC_FAMILY_NXP_MCX

soc/nxp/mcx/Kconfig.soc

@@ -1,10 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_FAMILY_NXP_MCX
-	bool
-
-config SOC_FAMILY
-	default "nxp_mcx" if SOC_FAMILY_NXP_MCX
-
 rsource "*/Kconfig.soc"

soc/nxp/mcx/mcxa/Kconfig

@@ -1,7 +1,7 @@
 # Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXA
+config SOC_FAMILY_MCXA
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 	select CLOCK_CONTROL
 	select ARM

soc/nxp/mcx/mcxa/Kconfig.defconfig

@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_MCXA
+if SOC_FAMILY_MCXA
 
 config CORTEX_M_SYSTICK
 	default n if MCUX_LPTMR_TIMER
@@ -18,4 +18,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
-endif # SOC_SERIES_MCXA
+endif # SOC_FAMILY_MCXA

soc/nxp/mcx/mcxa/Kconfig.soc

@@ -1,28 +1,27 @@
 # Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXA
+config SOC_FAMILY_MCXA
 	bool
-	select SOC_FAMILY_NXP_MCX
 
-config SOC_SERIES
-	default "mcxa" if SOC_SERIES_MCXA
+config SOC_FAMILY
+	default "mcxa" if SOC_FAMILY_MCXA
 
 config SOC_MCXA153
 	bool
-	select SOC_SERIES_MCXA
+	select SOC_FAMILY_MCXA
 
 config SOC_MCXA156
 	bool
-	select SOC_SERIES_MCXA
+	select SOC_FAMILY_MCXA
 
 config SOC_MCXA166
 	bool
-	select SOC_SERIES_MCXA
+	select SOC_FAMILY_MCXA
 
 config SOC_MCXA276
 	bool
-	select SOC_SERIES_MCXA
+	select SOC_FAMILY_MCXA
 
 config SOC
 	default "mcxa153" if SOC_MCXA153

soc/nxp/mcx/mcxc/Kconfig

@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXC
+config SOC_FAMILY_MCXC
 	select ARM
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
@@ -19,7 +19,7 @@ config SOC_SERIES_MCXC
 	select SOC_EARLY_INIT_HOOK
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 
-if SOC_SERIES_MCXC
+if SOC_FAMILY_MCXC
 
 config MCXC_FLASH_CONFIG
 	bool "MCXC flash configuration field"

soc/nxp/mcx/mcxc/Kconfig.defconfig

@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_MCXC
+if SOC_FAMILY_MCXC
 
 config CORTEX_M_SYSTICK
 	default n if MCUX_LPTMR_TIMER
@@ -12,4 +12,4 @@ config NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 48000000
 
-endif # SOC_SERIES_MCXC
+endif # SOC_FAMILY_MCXC

soc/nxp/mcx/mcxc/Kconfig.soc

@@ -1,28 +1,27 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXC
+config SOC_FAMILY_MCXC
 	bool
-	select SOC_FAMILY_NXP_MCX
 
-config SOC_SERIES
-	default "mcxc" if SOC_SERIES_MCXC
+config SOC_FAMILY
+	default "mcxc" if SOC_FAMILY_MCXC
 
 config SOC_MCXC141
 	bool
-	select SOC_SERIES_MCXC
+	select SOC_FAMILY_MCXC
 
 config SOC_MCXC142
 	bool
-	select SOC_SERIES_MCXC
+	select SOC_FAMILY_MCXC
 
 config SOC_MCXC242
 	bool
-	select SOC_SERIES_MCXC
+	select SOC_FAMILY_MCXC
 
 config SOC_MCXC444
 	bool
-	select SOC_SERIES_MCXC
+	select SOC_FAMILY_MCXC
 
 config SOC
 	default "mcxc141" if SOC_MCXC141

soc/nxp/mcx/mcxn/Kconfig

@@ -1,7 +1,7 @@
 # Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXN
+config SOC_FAMILY_MCXN
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 	select CLOCK_CONTROL
 	select ARM
@@ -46,7 +46,7 @@ config SOC_MCXN236
 	select SOC_RESET_HOOK
 	select ARM_TRUSTZONE_M
 
-if SOC_SERIES_MCXN
+if SOC_FAMILY_MCXN
 
 if SOC_MCXN947 || SOC_MCXN547
 
@@ -100,4 +100,4 @@ endif # NXP_FLEXSPI_BOOT_HEADER
 
 rsource "../../common/Kconfig.flexspi_xip"
 
-endif # SOC_SERIES_MCXN
+endif # SOC_FAMILY_MCXN

soc/nxp/mcx/mcxn/Kconfig.defconfig

@@ -1,7 +1,7 @@
 # Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_MCXN
+if SOC_FAMILY_MCXN
 
 config CORTEX_M_SYSTICK
 	default n if MCUX_LPTMR_TIMER
@@ -37,4 +37,4 @@ config FLASH_FILL_BUFFER_SIZE
 config I2S_HAS_PLL_SETTING
 	default n
 
-endif # SOC_SERIES_MCXN
+endif # SOC_FAMILY_MCXN

soc/nxp/mcx/mcxn/Kconfig.soc

@@ -1,16 +1,15 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXN
+config SOC_FAMILY_MCXN
 	bool
-	select SOC_FAMILY_NXP_MCX
 
-config SOC_SERIES
-	default "mcxn" if SOC_SERIES_MCXN
+config SOC_FAMILY
+	default "mcxn" if SOC_FAMILY_MCXN
 
 config SOC_MCXN947
 	bool
-	select SOC_SERIES_MCXN
+	select SOC_FAMILY_MCXN
 
 config SOC_MCXN947_CPU0
 	bool
@@ -22,7 +21,7 @@ config SOC_MCXN947_CPU1
 
 config SOC_MCXN547
 	bool
-	select SOC_SERIES_MCXN
+	select SOC_FAMILY_MCXN
 
 config SOC_MCXN547_CPU0
 	bool
@@ -34,7 +33,7 @@ config SOC_MCXN547_CPU1
 
 config SOC_MCXN236
 	bool
-	select SOC_SERIES_MCXN
+	select SOC_FAMILY_MCXN
 
 config SOC
 	default "mcxn947" if SOC_MCXN947

soc/nxp/mcx/mcxw/Kconfig

@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXW
+config SOC_FAMILY_MCXW
 	select ARM
 	select CPU_CORTEX_M33
 	select CPU_CORTEX_M_HAS_DWT

soc/nxp/mcx/mcxw/Kconfig.defconfig

@@ -1,7 +1,7 @@
 # Copyright 2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_MCXW
+if SOC_FAMILY_MCXW
 
 config CORTEX_M_SYSTICK
 	default n if MCUX_LPTMR_TIMER
@@ -64,4 +64,4 @@ config NXP_RF_IMU
 endif # IEEE802154
 
 
-endif # SOC_SERIES_MCXW
+endif # SOC_FAMILY_MCXW

soc/nxp/mcx/mcxw/Kconfig.soc

@@ -1,20 +1,19 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MCXW
+config SOC_FAMILY_MCXW
 	bool
-	select SOC_FAMILY_NXP_MCX
 
-config SOC_SERIES
-	default "mcxw" if SOC_SERIES_MCXW
+config SOC_FAMILY
+	default "mcxw" if SOC_FAMILY_MCXW
 
 config SOC_MCXW716C
 	bool
-	select SOC_SERIES_MCXW
+	select SOC_FAMILY_MCXW
 
 config SOC_MCXW727C
 	bool
-	select SOC_SERIES_MCXW
+	select SOC_FAMILY_MCXW
 
 config SOC_MCXW727C_CPU0
 	bool

soc/nxp/mcx/soc.yml

@@ -1,36 +1,34 @@
 family:
-- name: nxp_mcx
-  series:
-  - name: mcxn
-    socs:
-    - name: mcxn947
-      cpuclusters:
-      - name: cpu0
-      - name: cpu1
-    - name: mcxn547
-      cpuclusters:
-      - name: cpu0
-      - name: cpu1
-    - name: mcxn236
-  - name: mcxc
-    socs:
-    - name: mcxc141
-    - name: mcxc142
-    - name: mcxc242
-    - name: mcxc444
-  - name: mcxa
-    socs:
-    - name: mcxa153
-    - name: mcxa156
-    - name: mcxa166
-    - name: mcxa276
-  - name: mcxw
-    socs:
-    - name: mcxw716c
-    - name: mcxw727c
-      cpuclusters:
-      - name: cpu0
-      - name: cpu1
+- name: mcxn
+  socs:
+  - name: mcxn947
+    cpuclusters:
+    - name: cpu0
+    - name: cpu1
+  - name: mcxn547
+    cpuclusters:
+    - name: cpu0
+    - name: cpu1
+  - name: mcxn236
+- name: mcxc
+  socs:
+  - name: mcxc141
+  - name: mcxc142
+  - name: mcxc242
+  - name: mcxc444
+- name: mcxa
+  socs:
+  - name: mcxa153
+  - name: mcxa156
+  - name: mcxa166
+  - name: mcxa276
+- name: mcxw
+  socs:
+  - name: mcxw716c
+  - name: mcxw727c
+    cpuclusters:
+    - name: cpu0
+    - name: cpu1
 runners:
   run_once:
     '--erase':