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8847 Commits

Author SHA1 Message Date
Aksel Skauge Mellbye
d85d3df323 dts: arm: silabs: Add Series 2 TIMER PWM 
Add binding and DT nodes for PWM using the Timer peripheral.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
 2025-06-25 14:07:40 +02:00
Aksel Skauge Mellbye
2a958aa53f dts: arm: silabs: Add Series 2 LETIMER PWM 
Add binding and DT nodes for PWM using the Low Energy Timer.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
 2025-06-25 14:07:40 +02:00
Peter Wang
55db18bc06 boards: frdm_mcxa166, frdm_mcxa276: add i3c support 
1. enable i3c driver and sensor p3t1755
2. verified samples/sensor/thermometer

Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
 2025-06-25 10:53:50 +02:00
Phi Tran
26f9fdf384 dts: renesas: update dts node in SoC layer to support pwm on RX130. 
This commit to add node on RX130 dts to support pwm with MTU modules.

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
 2025-06-25 10:52:34 +02:00
Phi Tran
d8ab33ae96 drivers: pwm: Add support for PWM driver on RSK_RX130_512KB 
This is initial commit to support PWM driver
on Renesas RX130 with MTU modules.

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
 2025-06-25 10:52:34 +02:00
Hou Zhiqiang
71c321dbed dts: arm64: nxp: imx91: add TPM device tree nodes 
Added TPM device tree nodes.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
 2025-06-25 10:49:03 +02:00
Jiafei Pan
d5b9e74476 boards: imx8mp_evk: a53: enable FlexCAN on the board 
Added dts nodes of FlexCAN1 and FlexCAN2 in SoC dts.
Added dts nodes and overlay in imx8mp_evk board.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
 2025-06-25 09:52:56 +02:00
Jiafei Pan
298cfdac88 dts: bindings: flexcan: add rdc property 
Add rdc property to let RDC driver to configure RDC for flexcan.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
 2025-06-25 09:52:56 +02:00
Thao Luong
040e4e85be dts: arm: renesas: ra2: Add support RA2L1 80 pins, 64 pins and 48 pins 
Add support for RA2L1 80 pins, 64 pins and 48 pins packages.

Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
 2025-06-25 09:52:23 +02:00
Thao Luong
6fedc33354 dts: arm: renesas: Add trng, spi, pwm, counter, i2c, adc and dac for ra2l1 
Add support for trng, spi, pwm (gpt), counter (agt), i2c (iic_master),
adc and dac for RA2L1.
Add external interrupt for RA2L1.

Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
 2025-06-25 09:52:23 +02:00
Benjamin Cabé
0d3f294338 dts: bindings: sensor: update brcm,afbr-s50 example snippet 
Update the dt snippet so that it includes all the required properties

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
 2025-06-24 20:06:14 -10:00
Yongxu Wang
0bf39e8213 drivers: dma: Update NXP EDMA driver for version 5 
1. The edma version 5 share one driver with edma 4.
2. Edma5 tcd structure some difference, Use tcd type to distinguish,
   and Edma5 uses 64 bytes for alignment instead of 32.
3. Some platforms have some address offsets for certain memory
   when processing from a DMA perspective, such as imx95 cm7 TCM,
   so add offset processing.

Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
 2025-06-24 20:02:35 -10:00
Yongxu Wang
774370a1d7 boards: nxp: imx95_evk_mimx9596_m7: add uart dma support 
- verify in uart_async_api test case.

Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
 2025-06-24 20:02:35 -10:00
Youssef Zini
be12fa104f dts: arm: st: stm32mp2_m33.dtsi: add uart/usart 
Add UART/USART nodes in non-secure context to the device tree for
STM32MP2 SoC.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
 2025-06-24 15:37:57 -05:00
Youssef Zini
98b4f4e62e dts: arm: st: stm32mp2_m33.dtsi: add rctl node 
Add the reset controller node to the STM32MP2 M33 device tree source
file.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
 2025-06-24 15:37:57 -05:00
Lucien Zhao
fc293803f3 dts: arm: nxp: support sai instances on rt700 cm33 cpu0 
add 3 sai instances on cm33 cpu0
add pinmux-cells in lpc-syscon.yaml

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
 2025-06-24 15:35:07 -05:00
Miguel Gazquez
798dc5c976 soc: wch: Add packages for the ch32v303 
Add the different packages of the CH32V303

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
 2025-06-24 15:34:42 -05:00
Miguel Gazquez
de0ef827cd dts: wch: add gpioe bank to ch32v303 
Adds the gpioe bank to the ch32v303 devicetree.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
 2025-06-24 15:34:42 -05:00
Miguel Gazquez
1f5a281e9b dts: wch: fix ngpios for some WCH SoCs 
The CH32V20x and CH32V30x SoCs have 16 pins per GPIO bank, but in the
devicetree, `ngpios` was incorrectly set to 8.
Fix the devicetrees by setting the correct value.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
 2025-06-24 15:34:42 -05:00
Yunshao Chiang
5a2765da26 drivers: comparator: add it51xxx_evb analog comparator driver 
Add analog comparator driver for ITE it51xxx chip.

Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
 2025-06-24 15:33:17 -05:00
Khaoula Bidani
29c7500360 dts: arm: st: u3: add spi 
Add SPI support to STM32U3

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
 2025-06-24 14:22:58 +02:00
Tien Nguyen
cff21ea2be dts: arm: renesas: Add support for Renesas RZ/V2H R8 core 
Add devicetree to support for Renesas RZ/V2H R8 core

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
 2025-06-24 14:22:43 +02:00
Tien Nguyen
b8215ec539 dts: bindings: Add CPU device bindings for Cortex-R8 
This commit adds device bindings for Cortex-R8

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
 2025-06-24 14:22:43 +02:00
Fabio Baltieri
f2934c8b8a bindings: uart-bridge: add missing base include 
Add missing base include for the uart-bridge binding.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
 2025-06-24 14:19:24 +02:00
Phi Tran
3fa9495172 drivers: gpio: add gpio interrupt support for RX130 
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
 2025-06-24 14:18:41 +02:00
Phi Tran
da38a779ea drivers: external interrupt: add external interrupt support for RX130 
Add support for external interrupt on RX130.

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
 2025-06-24 14:18:41 +02:00
Tatsuya Ogawa
5560c9f12a drivers: interrupt_controller: Add interrupt controller support for RX130 
Add interrupt controller driver support for RX130 series

Signed-off-by: Tatsuya Ogawa <tatsuya.ogawa.nx@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
 2025-06-24 14:18:41 +02:00
Anıl Kara
34b06f89fe dts: arm: adi: Add timer nodes to max32657 
Add nodes timer0 to timer5. Add pwm and counter subnodes.

Signed-off-by: Anıl Kara <anil.kara@analog.com>
 2025-06-24 09:15:07 +02:00
Laurentiu Mihalcea
44f346e6d7 dts: bindings: dai-esai: allow pinctrl-related properties 
Allow pinctrl-related properties to be specified in the ESAI
DT node.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
 2025-06-24 09:13:45 +02:00
Laurentiu Mihalcea
1f483b37ea drivers: clock_control: mcux_ccm: support QM/QXP's ESAI/AUD_PLL1 clocks 
Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
 2025-06-24 09:13:45 +02:00
Francois Ramu
aac2c5c568 dts: arm: stm32 reg definition for the st,stm32-qspi compatible 
The st,stm32-qspi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32F412, stm32F7, stm32L4, stm32H7, stm32WB series.
qspi is addressing max 256 MBytes from 0x90000000.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
 2025-06-24 09:13:33 +02:00
Francois Ramu
ec9f74f57d dts: bindings: flash controller size of the stm32 qspi nor 
This change adds the size in Bits of the flash nor memory
for the st,stm32-qspi-nor compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
 2025-06-24 09:13:33 +02:00
Peter Fecher
f559f588da dts: nxp_imx8ml_m7: Add i2c Devicetree nodes 
Add i2c DeviceTree nodes for use with the
Coretex M7 on the NXP imx8ml.

Signed-off-by: Peter Fecher <p.fecher@phytec.de>
 2025-06-24 09:13:04 +02:00
Benjamin Perseghetti
4d91f6c3ed drivers: sensor: icm42688 enable fifo-hires in DT 
Allow setting fifo-highres from DT, also unify the
naming of all registers and expand to a more complete list.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
 2025-06-23 16:29:32 -05:00
Benjamin Perseghetti
5c9d6d44f3 drivers: sensor: icm42688 add axis_align in DT 
Introduces the ability to set static axis
alignment of a sensor from DT params.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
 2025-06-23 16:29:32 -05:00
Duy Nguyen
92a631e836 drivers: i2c: Add support i2c driver for Renesas RX MCU 
Add initial support for i2c on Renesas RX MCU
This driver is controlling the RIIC HW of RX MCU for i2c bus
interface on Zephyr
Only master mode is supported

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
 2025-06-23 16:26:51 -05:00
Khaoula Bidani
7fe048cae1 dts: arm: st: u3: add i2c 
Add I2C nodes to STM32U3

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
 2025-06-23 12:33:52 -07:00
Sergei Ovchinnikov
34188c4336 dts: bindings: add npm1304 extracting common from npm1300 
Add nPM1304 device tree bindings. Extract the properties common to
nPM1300 and nPM1304 into npm13xx-common files.

Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
 2025-06-23 16:19:43 +01:00
Dave Joseph
fb3c562644 dts: arm: ti TISCI DMSC support for AM2434 EVM 
Device tree edits to add DMSC system controller support for
AM2434 EVM. This includes the addition system-controller and
secure-proxy mailbox nodes in arm46x_main.dtsi.

Signed-off-by: Dave Joseph <d-joseph@ti.com>
 2025-06-23 15:54:34 +01:00
Dave Joseph
95c20c338c drivers: firmware: TISCI driver support 
Added TISCI driver for supported devices using the binding ti,k2g-sci.
This is used to communicate via the secury proxy channel for clock,
resource and power domain management.
Refer: https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/TISCI_header.html

Signed-off-by: Dave Joseph <d-joseph@ti.com>
 2025-06-23 15:54:34 +01:00
Bjarki Arge Andreasen
4c3671aea3 dts: vendor: nordic: nrf54h20.dtsi: disable cpurad_hsfll 
The cpurad_hsfll is not yet supported by the NRFS DVFS service,
disable it to prevent driver from being loaded.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
 2025-06-23 15:47:01 +01:00
Hao Luo
4a9412b5d4 drivers: adc: add dma support for ambiq adc driver 
This commit adds dma support for ambiq adc driver

Signed-off-by: Hao Luo <hluo@ambiq.com>
 2025-06-23 15:45:44 +01:00
Khaoula Bidani
022ad6839a dts: arm: st: u3: add gpdma 
Add GPDMA support to STM32U3

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
 2025-06-23 13:42:19 +02:00
Jamie McCrae
2a674977dd dts: vendor: nordic: nrf54l*: Fix GPREGRET register addresses 
Fixes these peripheral's to have the correct addresses

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
 2025-06-23 09:46:33 +02:00
Tony Han
685375fbc5 dts: microchip: sam: add I2C (FLEXCOM submodule) nodes to sama7g5.dtsi 
Each of the 12 FLEXCOM instances supports working in TWI (I2C) mode.

Signed-off-by: Tony Han <tony.han@microchip.com>
 2025-06-22 18:44:04 -07:00
Tony Han
6243ff43c4 dts: microchip: sam: add all USART (FLEXCOM submodule) to sama7g5.dtsi 
SAMA7G5 has 12 FLEXCOM instances and each of them supports working in
USART mode.

Signed-off-by: Tony Han <tony.han@microchip.com>
 2025-06-22 18:44:04 -07:00
Tamas Jozsi
2c43a00f65 boards: fix Bluetooth LE support on the SparkFun ThingPlus Matter MGM240 
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
 2025-06-21 15:31:36 +02:00
Tamas Jozsi
e4dc7c9fb1 soc: silabs: Add support for the MGM240SD22VNA 
Also introduce the framework to support other
Silicon Labs modules.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
 2025-06-21 15:31:36 +02:00
Camille BAUD
8c385be293 soc: bflb: enable clock_control for bl60x 
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-06-21 10:40:20 +02:00
Camille BAUD
46b5d05ae1 drivers: clock_control: Introduce bl60x clock driver 
This introduces a clock_control driver for bl60x

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-06-21 10:40:20 +02:00