dts: arm: renesas: Add support for Renesas RZ/V2H R8 core
Add devicetree to support for Renesas RZ/V2H R8 core Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This commit is contained in:
Tien Nguyen
Benjamin Cabé
parent
9688b7510f
commit
cff21ea2be
388
dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi
Normal file
388
dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <arm/armv7-r.dtsi>
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#include <mem.h>
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#include <freq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r8";
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reg = <0>;
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clock-frequency = <DT_FREQ_M(800)>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&gic>;
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arch_timer: timer@12c10200 {
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compatible = "arm,armv8-timer";
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status = "okay";
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interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3";
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
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reg = <0x12c10200 0x1C>;
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label = "arch_timer";
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};
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gic: interrupt-controller@12c11000 {
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compatible = "arm,gic-v1", "arm,gic";
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reg = <0x12c11000 0x1000>, <0x12c10100 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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pinctrl: pin-controller@10410000 {
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compatible = "renesas,rzv-pinctrl";
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reg = <0x10410000 DT_SIZE_K(64)>;
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reg-names = "pinctrl";
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gpio: gpio-common {
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compatible = "renesas,rz-gpio-int";
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 354 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 355 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 356 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 357 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 358 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 360 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 361 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 362 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 363 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 364 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 366 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 367 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 368 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 369 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 370 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 372 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 373 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 376 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 378 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 379 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 380 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 381 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 382 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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gpio0: gpio@0 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x0>;
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status = "disabled";
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};
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gpio1: gpio@100 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <6>;
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reg = <0x100>;
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status = "disabled";
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};
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gpio2: gpio@200 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <2>;
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reg = <0x200>;
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status = "disabled";
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};
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gpio3: gpio@300 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x300>;
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status = "disabled";
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};
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gpio4: gpio@400 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x400>;
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status = "disabled";
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};
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gpio5: gpio@500 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x500>;
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status = "disabled";
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};
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gpio6: gpio@600 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x600>;
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status = "disabled";
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};
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gpio7: gpio@700 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x700>;
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status = "disabled";
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};
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gpio8: gpio@800 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x800>;
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status = "disabled";
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};
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gpio9: gpio@900 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0x900>;
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status = "disabled";
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};
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gpio10: gpio@a00 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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reg = <0xa00>;
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status = "disabled";
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};
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gpio11: gpio@b00 {
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compatible = "renesas,rz-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <6>;
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reg = <0xb00>;
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status = "disabled";
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};
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};
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};
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sci0: sci0@12800c00 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12800c00 0x400>;
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channel = <0>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 115 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 116 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci1: sci1@12801000 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12801000 0x400>;
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channel = <1>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 121 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 122 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci2: sci2@12801400 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12801400 0x400>;
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channel = <2>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 127 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 128 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci3: sci3@12801800 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12801800 0x400>;
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channel = <3>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 133 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 134 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci4: sci4@2801c00 {
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compatible = "renesas,rz-sci-b";
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reg = <0x2801c00 0x400>;
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channel = <4>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 139 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 140 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci5: sci5@12802000 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12802000 0x400>;
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channel = <5>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 145 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 146 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci6: sci6@12802400 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12802400 0x400>;
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channel = <6>;
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interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 151 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 152 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci7: sci7@12802800 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12802800 0x400>;
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channel = <7>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 157 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 158 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci8: sci8@12802c00 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12802c00 0x400>;
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channel = <8>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 163 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 164 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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sci9: sci9@12803000 {
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compatible = "renesas,rz-sci-b";
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reg = <0x12803000 0x400>;
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channel = <9>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 169 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 170 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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status = "disabled";
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uart {
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compatible = "renesas,rz-sci-b-uart";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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};
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};
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