UARTE20 and UARTE21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Add a overlay for the nucleo_c092 testing usart4 and dma
channels 6 and 7. These are all not available in smaller STM32C0 SoCs.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Remove duplicated test configuration after
nrf54l20pdk/nrf54l20/cpuxxx was renamed to
nrf54lm20dk/nrf54lm20a/cpuxxx.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Remove duplicated test configuration after
nrf54l20pdk/nrf54l20/cpuxxx was renamed to
nrf54lm20dk/nrf54lm20a/cpuxxx.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Remove duplicated test configuration after
nrf54l20pdk/nrf54l20/cpuxxx was renamed to
nrf54lm20dk/nrf54lm20a/cpuxxx.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Remove duplicated test configuration after
nrf54l20pdk/nrf54l20/cpuxxx was renamed to
nrf54lm20dk/nrf54lm20a/cpuxxx.
Reorganize testcase.yaml to make it easier to maintain.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Remove duplicated test configuration after
nrf54l20pdk/nrf54l20/cpuxxx was renamed to
nrf54lm20dk/nrf54lm20a/cpuxxx.
Add test on fast instance uart00 on nrf54lm20dk.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
This target can also run this tests, we just overlays including
the ones for the real boards.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Extends support and adds new overlays.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
With the current configuration, we encounter a user setting error
during the test with the log:
"Wrong number of bytes received, got: 2, expected: 3."
Workaround:
Increase the clock frequency to enable faster data transmission
and avoid user setting errors.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Since nucleo_f746zg has NOCACHE_MEM defined
(related to test cases drivers.uart.async_api.nocache_mem
and drivers.uart.async_api.nocache_mem_dt.nucleo_f746zg),
the TX buffer should be placed in a non-cacheable memory region
for the uart_async_var_buf_length testsuite to pass.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add UART test overlays for Nucleo U385RG-Q board.
Remove non serial boot conf file since they are now unnecessary.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This fixes the case where uart_tx() called from tx callback
fill UART output fifo and immediately execute callback again.
This can happen when hardware does not have interrupt for
output FIFO empty and there is no non-blocking way to tell
that transfer finished.
For such case as soon as output FIFO is filled there is
interrupt that informs that more data can be transmitted.
For hardware with 32 byte fifo callback was seen to be
executed recursively 3 times.
That would not be a problem if chained_write_next_buf
was set BEFORE next call uart_tx().
Additionally semaphore max value is increased to 2
to accommodate such case.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg.xr@bp.renesas.com>
clock control is required for "fast instances" so assert clock
is enabled alongside PM DEVICE RUNTIME. Update UART tests to
reflect this requirenment.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add test which is using two independent UART devices. Validate behavior of
asynchronous API.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
We fix 2 issues:
First issue: __aligned attribute is in bytes
second issue: we should align depending on the platform
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add overlays required to run the test on:
- nrf54l09pdk/nrf54l09/cpuflpr,
- nrf54l20pdk/nrf54l20/cpuflpr.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Explicitly disable device runtime PM since this test is expecting
it to be disabled and there are SoC now that turns on it by default.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Remove the support of the Nucleo WBA52CG board since it is NRND
(Not Recommended for New Design) and it is not supported anymore
in the STM32CubeWBA from version 1.1.0 (July 2023).
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
When CONFIG_COVERAGE is enabled then performance is degraded.
In that case higher baudrates shall be avoided because CPU may
not have enough time to handle UART interrupts. Limit baudrate
to 115200 when CONFIG_COVERAGE=y.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add some overlay files for the silabs xg29_rb4412a board to enable tests
on the board. Also add the platform to some testcase.yaml files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The UART test for USART needs to move the console to an EUSART instance
in order to free up USART0 for the test. Since EUSART1 is configured for
SPI use by the board DTS, use EUSART0 for console.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Rename the driver from uart_native_posix to uart_native_pty.
Including renaming the DTS compatible, and kconfig options, deprecating
the old ones.
And refactor the driver, generalizing it, so we can have any number of
instances.
Note that, unfortunately generalizing to N instances cannot be done
without a degree of backwards compatibility breakage: This driver was
born with all its configuration and selection of the instances based on
kconfig.
When the driver was made to use DT, it was done in a way that required
both DT and kconfig needing to manually coherently enable the 2nd UART.
This has now been fixed, which it means only DT is used to decide how
many instances are avaliable, and UART_NATIVE_POSIX_PORT_1_ENABLE is
just ignored.
Including:
* Deprecate UART_NATIVE_WAIT_PTS_READY_ENABLE: the options is always on
now as it has no practical drawbacks.
* Deprecate UART_NATIVE_POSIX_PORT_1_ENABLE: DTS intanciation defines it
being available now.
* Rename a few functions and in general shorten pseudo-tty/pseudo-
terminal to PTY instead of PTTY.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit fixes the following
bug.Issue link:
https://github.com/zephyrproject-rtos/
zephyr/issues/86399.
Some users reported data access
violations due to the qualifier.
Removing static ensures proper memory
alignment and avoids potential
memory access issues.
Signed-off-by: S Swetha <s.swetha@intel.com>
This commit disables CONFIG_TEST_USERSPACE in
intel_rpl_s_crb.conf of uart_async_api
testcase.Enabling this config introduces
restrictions that interfere with cacheable
regions by blocking access and modifying
cache attributes.By disabling this
configuration, the following issues
are resolved:
-Cacheable region retain their attributes.
-Execution and data transactions work without
restrictions.
-System behavior align with expected
configuration in privileged mode.
-Some code primarily relying on non-cache
region continues to work.
This change is neccessary to ensure
cachebale memory regions function as intended
without interferance from user mode restrictions.
Signed-off-by: S Swetha <s.swetha@intel.com>
This commit aligns the buffers to 32 bytes in
uart_async_api testcases.This is because most
of the platform DMA operations are aligned to
32 bytes.This ensures proper memory alignment
for cache handling and avoid potential
unaligned access issues.
Signed-off-by: S Swetha <s.swetha@intel.com>
Add UART test overlays for Nucleo N657x0-Q and STM32N6570 DK boards.
Remove non serial boot conf file since they are now unnecessary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
