bartoszek/zephyr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5594de49ea
zephyr/tests/drivers/clock_control
History
Jatty Andriean 3eea17c5de tests: drivers: clock_control: Add PLL fracn test 
Added a test case that generates a 160 MHz system clock
using a 16777216 Hz HSE clock and also using a 16 MHz HSI

Signed-off-by: Jatty Andriean <jandriea@outlook.com>
2023-09-26 15:06:56 +02:00
..
adsp_clock adsp: Rename cpu clock related functions 2023-06-20 14:19:13 -04:00
clock_control_api samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
fixed_clock drivers: clock_control: Add clock_fixed_rate driver 2023-07-03 12:49:27 +02:00
nrf_clock_calibration samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
nrf_lf_clock_start tests: drivers: clock_control: nrf_lf_clock_start: Clean up 2023-09-13 11:36:30 +02:00
nrf_onoff_and_bt samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
onoff samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
stm32_clock_configuration tests: drivers: clock_control: Add PLL fracn test 2023-09-26 15:06:56 +02:00