Jatty Andriean 3eea17c5de tests: drivers: clock_control: Add PLL fracn test ... Added a test case that generates a 160 MHz system clock using a 16777216 Hz HSE clock and also using a 16 MHz HSI Signed-off-by: Jatty Andriean <jandriea@outlook.com>		2023-09-26 15:06:56 +02:00
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stm32_common_core	samples, tests: convert string-based twister lists to YAML lists	2023-05-10 09:52:37 +02:00
stm32_common_devices	tests: drivers: clock_control: stm32 common: also test get_status	2023-04-17 11:33:15 +02:00
stm32h5_core	tests: drivers: clock_control of the stm32h5 core	2023-05-15 13:09:46 +02:00
stm32h7_core	samples, tests: convert string-based twister lists to YAML lists	2023-05-10 09:52:37 +02:00
stm32h7_devices
stm32u5_core	tests: drivers: clock_control: Add PLL fracn test	2023-09-26 15:06:56 +02:00
stm32u5_devices
stm32wba_core	tests/drivers/clock_control: Add tests for stm32wba_core	2023-07-20 16:25:02 +02:00