Mahesh Mahadevan 9ae310b923 soc: nxp_mxrt7xx: Fix cache implementation for CPU0 ... This SoC has an external XCACHE controller for CPU0 instruction and data bus. Add code to enable the data cache. Instruction cache is already enabled by SystemInit. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>		2025-02-13 01:14:20 +01:00
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imxrt5xx	soc: nxp: imxrt5xx: enable Flexcomm12 clock for SPI	2025-01-07 15:57:50 +01:00
imxrt6xx	soc: nxp: Make clock init weak and global	2025-02-05 10:20:41 +01:00
imxrt7xx	soc: nxp_mxrt7xx: Fix cache implementation for CPU0	2025-02-13 01:14:20 +01:00
imxrt10xx	soc: nxp: Make clock init weak and global	2025-02-05 10:20:41 +01:00
imxrt11xx	soc: nxp: Make clock init weak and global	2025-02-05 10:20:41 +01:00
imxrt118x	soc: nxp: imxrt118x: add M7 MPU configuration	2025-02-11 22:03:48 +01:00
boot_header.ld	soc: nxp: imxrt: imxrt7xx: add rt7xx soc files	2025-01-14 17:56:53 +01:00
CMakeLists.txt	soc: nxp: imxrt118x: add M7 MPU configuration	2025-02-11 22:03:48 +01:00
container.ld	soc: nxp: imxrt: add imxrt118x series and update related files	2024-08-15 14:51:02 -04:00
flexspi_nor_config.h	soc: nxp: Remove RT1061 and RT1051 refs	2024-08-22 09:14:24 +02:00
Kconfig	soc: nxp: imxrt: imxrt7xx: add rt7xx soc files	2025-01-14 17:56:53 +01:00
Kconfig.defconfig	boards|soc: remove selection of ENTROPY_GENERATOR	2024-12-19 17:53:37 +01:00
Kconfig.soc
Kconfig.sysbuild	soc: nxp: imxrt: add CONFIG_SECOND_CORE_MCUX_LAUNCHER	2025-01-07 20:34:26 +01:00
mpu_regions.c
soc.yml	soc: imxrt: add mimxrt1189 flashing configuration	2025-01-20 11:16:34 +01:00
sysbuild.cmake	soc: nxp: imxrt: add CONFIG_SECOND_CORE_MCUX_LAUNCHER	2025-01-07 20:34:26 +01:00
usb.ld