Mahesh Mahadevan 9ae310b923 soc: nxp_mxrt7xx: Fix cache implementation for CPU0 ... This SoC has an external XCACHE controller for CPU0 instruction and data bus. Add code to enable the data cache. Instruction cache is already enabled by SystemInit. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>		2025-02-13 01:14:20 +01:00
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common	soc: nxp: imxrt: imxrt7xx: add rt7xx soc files	2025-01-14 17:56:53 +01:00
imx	soc: nxp: add SoC imx91 support	2025-02-11 22:08:59 +01:00
imxrt	soc: nxp_mxrt7xx: Fix cache implementation for CPU0	2025-02-13 01:14:20 +01:00
kinetis	soc: nxp: Make clock init weak and global	2025-02-05 10:20:41 +01:00
layerscape	soc: Remove re-defining some defined types	2024-11-18 07:41:23 -05:00
lpc	soc: nxp: Make clock init weak and global	2025-02-05 10:20:41 +01:00
mcx	soc: nxp: mcxw: Enable RTT Support	2025-02-07 17:47:55 +01:00
rw	wifi: nxp: kconfig: decouple dependency of soft AP	2025-02-12 09:40:38 +01:00
s32	arch: arm: rename CPU_HAS_NXP_MPU to align with binding	2024-12-06 22:23:06 +01:00