This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Decouple dependency of CONFIG_NXP_WIFI_SOFTAP_SUPPORT.
Add wifi defconfig to set default kconfig options when soft AP
enabled.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
The i.MX 91 SoC’s integrated EdgeLock® Secure Enclave provides
security features including lifecycle management, tamper detection,
secure boot and a simplified path to certifications. The i.MX 91
family features an Arm® Cortex®-A55 running at up to 1.4GHz,
support for modern LPDDR4 memory to enable platform longevity,
dual Gigabit Ethernet and dual USB ports, along with a rich set
of peripherals targeting medical, industrial and consumer IoT
market segments.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Make clock init functions in SOC level weak and global so they can be
overriden by board/app level.
Ideally these should have been put at board level but for now just make
them weak so they can be overriden without breaking anything.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The current soc clock_init only configures the FlexSPI1 interface and
not the FlexSPI2.
This Commit adds the clock configuration for the second FlexSPI
in case one boots from the FlexSPI2.
Signed-off-by: Felix Schramek <felix.schramek@gmail.com>
nxp_nbu_init extern definition is under CONFIG_NXP_RW6XX_BOOT_HEADER
and this produces an implicite definition warning when
the Kconfig is disabled. This is the case when both BLE Kconfig
and MCUboot bootloader Kconfig are enabled.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
The clock source for LPUART0 for the MCXC family is already
initialized in the corresponding soc.c -> clock_init().
Initialization for LPUART1 is missing. This is however
necessary if a user wants to configure LPUART1 as the default
console output.
Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
A problem was discovered during development: the
electrical characteristics of the pins were not
set according to the device tree settings.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the BT_LONG_WQ_STACK stack size for peripheral_sc_only sample,
and the SYSTEM_WORKQUEUE stack size for ibeacon sample.
Signed-off-by: Jasen Liu <jasen.liu@nxp.com>
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the BT_LONG_WQ_STACK stack size for peripheral_sc_only sample,
and the SYSTEM_WORKQUEUE stack size for ibeacon sample.
Signed-off-by: Jasen Liu <jasen.liu@nxp.com>
- Adds a flash runner configuration for mimxrt1189,
used for sysbuild multi-image projects.
- Avoid unwanted multiple erases and resets.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The CM33 has a XCACHE controller to manage the External
cache. Remove unused Kconfigs as we can use Zephyr API's
to manage the CM33 cache,
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit adds MBOX device tree entry for MCXN947.
Adds support for MCXN in NXP ipm and mbox drivers.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the main stack size for common samples, but also the shell
stack size for samples calling bt API from the shell thread like the
bt shell.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the main stack size for common samples, but also the shell
stack size for samples calling bt API from the shell thread like the
bt shell.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
M33 early init for GPIO for secure access configuration,
so that driver can operate pins.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Chunlei Xu <chunlei.xu@nxp.com>
add lpspi clock enablement code
DMA3/4 access different domain is controlled by TRDC, release all
the domain access permission for DMA3/4, and add privilege and secure
information in dma access request signal by DAC module
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This change adds support for segger rtt, similar to other supported
soc's. This was lacking when evaluating tracing.
Without this addition the system fails to build, indicating that
HAS_SEGGER_RTT is missing. Adding CONFIG_HAS_SEGGER_RTT in prj.conf is
not allowed.
Signed-off-by: Bart De Vos <bart.devos@verhaert.com>
Add CONFIG_SECOND_CORE_MCUX_LAUNCHER. This Kconfig is only enabled when
using sysbuild targeting the Cortex-M4 core on the RT11xx series, and
results in loading a minimal application to the Cortex-M7 core that
boots the Cortex-M4 core. This makes developing on the M4 core simpler,
as the user can now simply target the core with sysbuild enabled and
flashing the application will work as expected.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Although I/DCACHE aren't included under cm33 architecture,
NXP design and integrate Code Cache/Sys Cache for cm33 to
speed up the core execution efficiency.
For the convenience of developers, we believe that software
developers can directly use Code/Sys Cache as arm's I/D Cache.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Enable CONFIG_GIC_SAFE_CONFIG by default for Cortex-A Core platforms
as the most targets are to run multiple OSes together with Zephyr on
different Cortex-A Cores.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add the DWARF v5 sections to the linker scripts of
imx, imxrt, acp_6_0 and xtensa_sample_controller.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Now that MbedTLS is capable of automatically enabling
CONFIG_ENTROPY_GENERATOR (when available), we can remove forced
enablements in boards|soc deconfig files.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
This is based on the introduction of a helper Kconfig symbol in
"subsys/random/Kconfig" which is named CSPRNG_AVAILABLE. When this is
enabled it means that there is a "zephyr,entropy" property defined in the
device-tree, therefore Mbed TLS can select ENTROPY_GENERATOR to allow
the platform specific driver to be included into the build.
This commit also changes other locations where CSPRNG_ENABLED was used
moving it to CSPRNG_AVAILABLE in order to solve dependency loop
build failures.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Enable CONFIG_HAS_MCUX_IGPIO because device driver CONFIG_GPIO_MCUX_IGPIO
depends on it, so that the driver can be enabled by dts nodes.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Combine BLE and 802.15.4 monolithic build under a single config to make
it less error prone.
The choice between a BLE/802.15.4 combo firmware and a BLE only firmware
is done depending on the Soc (like RW610 vs RW612).
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
- Adds a flash runner configuration for mcxn/c/a/w
used for sysbuild multi-image projects.
- Solves sysbuild issue with multiple resets and mass erases.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
