This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Make clock init functions in SOC level weak and global so they can be
overriden by board/app level.
Ideally these should have been put at board level but for now just make
them weak so they can be overriden without breaking anything.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The current soc clock_init only configures the FlexSPI1 interface and
not the FlexSPI2.
This Commit adds the clock configuration for the second FlexSPI
in case one boots from the FlexSPI2.
Signed-off-by: Felix Schramek <felix.schramek@gmail.com>
A problem was discovered during development: the
electrical characteristics of the pins were not
set according to the device tree settings.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Adds a flash runner configuration for mimxrt1189,
used for sysbuild multi-image projects.
- Avoid unwanted multiple erases and resets.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The CM33 has a XCACHE controller to manage the External
cache. Remove unused Kconfigs as we can use Zephyr API's
to manage the CM33 cache,
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
add lpspi clock enablement code
DMA3/4 access different domain is controlled by TRDC, release all
the domain access permission for DMA3/4, and add privilege and secure
information in dma access request signal by DAC module
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add CONFIG_SECOND_CORE_MCUX_LAUNCHER. This Kconfig is only enabled when
using sysbuild targeting the Cortex-M4 core on the RT11xx series, and
results in loading a minimal application to the Cortex-M7 core that
boots the Cortex-M4 core. This makes developing on the M4 core simpler,
as the user can now simply target the core with sysbuild enabled and
flashing the application will work as expected.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Although I/DCACHE aren't included under cm33 architecture,
NXP design and integrate Code Cache/Sys Cache for cm33 to
speed up the core execution efficiency.
For the convenience of developers, we believe that software
developers can directly use Code/Sys Cache as arm's I/D Cache.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add the DWARF v5 sections to the linker scripts of
imx, imxrt, acp_6_0 and xtensa_sample_controller.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Now that MbedTLS is capable of automatically enabling
CONFIG_ENTROPY_GENERATOR (when available), we can remove forced
enablements in boards|soc deconfig files.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
This is based on the introduction of a helper Kconfig symbol in
"subsys/random/Kconfig" which is named CSPRNG_AVAILABLE. When this is
enabled it means that there is a "zephyr,entropy" property defined in the
device-tree, therefore Mbed TLS can select ENTROPY_GENERATOR to allow
the platform specific driver to be included into the build.
This commit also changes other locations where CSPRNG_ENABLED was used
moving it to CSPRNG_AVAILABLE in order to solve dependency loop
build failures.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
On NXP RT1170 SOC, ADC ETC exists but it can not be enabled because
of dependency on HAS_MCUX_ADC_ETC.
Also, ADC ETC should only work with ADC together, there is no use
case to run it standalone.
Fixes:#81466
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
In the IOMUXC controller, the PDRV field uses 0b0 to set the pin drive
to high, and 0b1 to set the pin to normal drive. Fix the pinctrl_soc.h
definitions for the iMXRT11xx parts to use the correct setting for this
register, based on the documentation for the pin control binding
Note that for PDRV type pins, this commit effectively switches their
drive strength setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Many NXP socs had the following defconfig:
```
config PINCTRL_IMX
default y if HAS_IMX_IOMUXC
depends on PINCTRL
```
However, the PINCTRL_IMX option already has:
```
config PINCTRL_IMX
bool "Pin controller driver for iMX MCUs"
depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED
depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
default y
help
Enable pin controller driver for NXP iMX series MCUs
```
So the soc level defconfigs are redundant.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
add flexspi.c file to get flexspi clock rate.
Enable flexspi1 clock if don't boot from flash.
Use custom fixed mpu_regions.c file to config MPU for CM7
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
When option ARM_MPU is disabled exclude soc\nxp\imxrt\mpu_regions.c.
It is needed to remove constraints of SRAM and FLASH size.
Fixes#70920
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
As for the IMX SOCs all the lines removed in this commit were
actually commented out so there's basically no change in code
behavior expected here.
The only affected SOCs family is therefore the Kinetis one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
RT11xx SOC init should check to see if the zephyr flash node is
set to a device on the FLEXSPI bus to determine if the part is running
in XIP mode. This check was incorrect, so the FLEXSPI was being
reclocked in XIP mode to 24 MHz. Fix this check so the FlexSPI is not
downclocked.
Fixes#75702
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
- add ITCM definitions (for LinkServer) in board.cmake
- update of soc.c to support RAM images (stack pointer)
- doc update
Change applies to both versions of the MIMXRT1170 EVK
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
IMXRT1062 bootrom reads boothdr initial vector table
from 0x60001000. In the CMAKE scatter linker scripts we put multiple
sections at offset 0x1000 in the rom. In linkers other than LD, we are
not guaranteed a particular order when placing these.
If we specify FIRST we can count on the .ivt coming first. The other
positions aren't as crucial.
From IMXRT1060RM.pdf 9.7.1
> The location of the IVT is the only fixed requirement by the ROM.
> The remainder or the image memory map is flexible and
> is determined by the contents of the IVT.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Update RT5xx and RT6xx clock init to add the code
to set the I3C dividers. This code has been moved
from the I3C driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Reverts bus clock settings. Follows MCUXpresso SDK clock settings, and
sets to output of SysPLL2 PFD3 at 198 MHz.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Imply CONFIG_INIT_AUDIO_PLL on nxp,dmic driver selection on
mimxrt685s/cm33. Make DMIC clock config dependent on the use of the
RT685's audio PLL.
Fixes a regression described in #77851.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Fix flexspi xip configuration issue regarding code relocation
due to the order of kconfig defaults being sourced
The flexspi setup was not being relocated to an on chip location
Also remove rt1060 conf file in flash common test which changes the
code relocation location to RAM, just keep as ITCM for all M7 which
as of now all have ITCM from NXP with flexspi.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
