Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
When building for an STM32K010xB MCU, there is a deprecated properties
warning, which should be fixed by this PR.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
PSL_IN pin select register is Vsby power-up reset. When the other
core-domain-reset reset the chip, PSL_IN3/4 don't set to GPIO. This
commit adds PSL_IN3/4 to the pin select list in NPCX devicetree. So
these pins can be set to GPIO when the other core-domain-reset.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
GPT base address in the devicetree for the RT11xx SOC series was
incorrect, this commit fixes it
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Include the mem-region bindings for the stm32 ccm nodes and set the name
in the current dtsi files.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Enable flexspi for RT11xx SOCs. This requires selecting the correct
KConfig symbol for the cortex m4 and m7 SOCs, as well as correcting an
error in the flexspi DTS node and updating the clock init for RT11xx
SOCs.
Note that in addition, the NXP hal must be updated to properly support
including the cache management driver for the Cortex M4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is currently no information available about the XIP
addresses for the nRF52840 and nRF5340.
Add this via a new 'reg' block in the relevant QSPI nodes, along with
names for the register blocks so they are easier to retrieve.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
GPIO10 was missing from RT11xx DTS, and is required to manage SD card
power. Enable this GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use nrfx_gpiote and nrfx_ppi allocators to allocate channels
at runtime instead of fixed, device-tree based allocation which
is harder to maintain.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add the USB On-The-Go Supplement, Revision 2.0 in the DTS
of the stm32u575 and stm32u585 devices
(not for the stm32U5 serie).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix register addresses in rt11xx SOC dts. Flexcan1 was defined with an
incorrect register address, and watchdog 3 was incorrectly labelled as
watchdog 1. Watchdog 2 should not be enabled, as it is only accessible
from code running in the trustzone context.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert all in-tree NXP FlexCAN instances from hardcoding the CAN bus
timing in time quanta to specifying a desired sample point of 87.5% as
recommended by CAN in Automation (CiA).
This allows for the CAN driver to calculate the optimal time quanta
based on the CAN clock and the requested CAN bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
