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dts: arm: Add devicetree files for STM32L010xB series microcontrollers

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This PR adds the devicetree file for supporting the STM32L010xB mcu.

Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
This commit is contained in:
Wouter Cappelle 2021-10-15 10:43:47 +02:00 committed by Christopher Friedt
parent 9f6246c325
commit 8cdc822954
8 changed files with 77 additions and 11 deletions
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9
dts/arm/st/l0/stm32l0.dtsi
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@ -285,15 +285,6 @@
#io-channel-cells = <1>;
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <3>;

0
dts/arm/st/l0/stm32l011.dtsi → dts/arm/st/l0/stm32l010.dtsi
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40
dts/arm/st/l0/stm32l010Xb.dtsi Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2021 Wouter Cappelle <wouter.cappelle@crodeon.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l0/stm32l010.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(20)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
timers22: timers@40011400 {
compatible = "st,stm32-timers";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
interrupts = <22 0>;
interrupt-names = "global";
status = "disabled";
label = "TIMERS_22";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
st,prescaler = <0>;
label = "PWM_22";
#pwm-cells = <3>;
};
};
};
};

2
dts/arm/st/l0/stm32l011X4.dtsi
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@ -5,7 +5,7 @@
*/
#include <mem.h>
#include <st/l0/stm32l011.dtsi>
#include <st/l0/stm32l010.dtsi>
/ {
sram0: memory@20000000 {

11
dts/arm/st/l0/stm32l053.dtsi
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@ -19,7 +19,16 @@
phys = <&otgfs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
status = "disabled";
label= "USB";
label = "USB";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
otgfs_phy: otgfs_phy {

9
dts/arm/st/l0/stm32l072.dtsi
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@ -41,4 +41,13 @@
#phy-cells = <0>;
label = "OTGFS_PHY";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
};

14
soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb Normal file
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@ -0,0 +1,14 @@
# ST Microelectronics STM32L010XX MCU
#
# Copyright (c) 2021 Wouter Cappelle <wouter.cappelle@crodeon.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_STM32L010XB
config SOC
default "stm32l010xb"
config NUM_IRQS
default 32
endif # SOC_STM32L010XB

3
soc/arm/st_stm32/stm32l0/Kconfig.soc
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@ -9,6 +9,9 @@ choice
prompt "STM32L0x MCU Selection"
depends on SOC_SERIES_STM32L0X
config SOC_STM32L010XB
bool "STM32L010XB"
config SOC_STM32L011XX
bool "STM32L011XX"