Extends support and adds new overlays.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
With the current configuration, we encounter a user setting error
during the test with the log:
"Wrong number of bytes received, got: 2, expected: 3."
Workaround:
Increase the clock frequency to enable faster data transmission
and avoid user setting errors.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Since nucleo_f746zg has NOCACHE_MEM defined
(related to test cases drivers.uart.async_api.nocache_mem
and drivers.uart.async_api.nocache_mem_dt.nucleo_f746zg),
the TX buffer should be placed in a non-cacheable memory region
for the uart_async_var_buf_length testsuite to pass.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add UART test overlays for Nucleo U385RG-Q board.
Remove non serial boot conf file since they are now unnecessary.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This fixes the case where uart_tx() called from tx callback
fill UART output fifo and immediately execute callback again.
This can happen when hardware does not have interrupt for
output FIFO empty and there is no non-blocking way to tell
that transfer finished.
For such case as soon as output FIFO is filled there is
interrupt that informs that more data can be transmitted.
For hardware with 32 byte fifo callback was seen to be
executed recursively 3 times.
That would not be a problem if chained_write_next_buf
was set BEFORE next call uart_tx().
Additionally semaphore max value is increased to 2
to accommodate such case.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg.xr@bp.renesas.com>
We fix 2 issues:
First issue: __aligned attribute is in bytes
second issue: we should align depending on the platform
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Remove the support of the Nucleo WBA52CG board since it is NRND
(Not Recommended for New Design) and it is not supported anymore
in the STM32CubeWBA from version 1.1.0 (July 2023).
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
When CONFIG_COVERAGE is enabled then performance is degraded.
In that case higher baudrates shall be avoided because CPU may
not have enough time to handle UART interrupts. Limit baudrate
to 115200 when CONFIG_COVERAGE=y.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add some overlay files for the silabs xg29_rb4412a board to enable tests
on the board. Also add the platform to some testcase.yaml files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The UART test for USART needs to move the console to an EUSART instance
in order to free up USART0 for the test. Since EUSART1 is configured for
SPI use by the board DTS, use EUSART0 for console.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit fixes the following
bug.Issue link:
https://github.com/zephyrproject-rtos/
zephyr/issues/86399.
Some users reported data access
violations due to the qualifier.
Removing static ensures proper memory
alignment and avoids potential
memory access issues.
Signed-off-by: S Swetha <s.swetha@intel.com>
This commit disables CONFIG_TEST_USERSPACE in
intel_rpl_s_crb.conf of uart_async_api
testcase.Enabling this config introduces
restrictions that interfere with cacheable
regions by blocking access and modifying
cache attributes.By disabling this
configuration, the following issues
are resolved:
-Cacheable region retain their attributes.
-Execution and data transactions work without
restrictions.
-System behavior align with expected
configuration in privileged mode.
-Some code primarily relying on non-cache
region continues to work.
This change is neccessary to ensure
cachebale memory regions function as intended
without interferance from user mode restrictions.
Signed-off-by: S Swetha <s.swetha@intel.com>
This commit aligns the buffers to 32 bytes in
uart_async_api testcases.This is because most
of the platform DMA operations are aligned to
32 bytes.This ensures proper memory alignment
for cache handling and avoid potential
unaligned access issues.
Signed-off-by: S Swetha <s.swetha@intel.com>
Add UART test overlays for Nucleo N657x0-Q and STM32N6570 DK boards.
Remove non serial boot conf file since they are now unnecessary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Test was staring a TX transfer and aborting it after 300 us from
the timer handler. Test was assuming that ongoing transfer will
not finish in those 300 us. This might not be true for higher
baudrates. Instead of using fixed timeout, a value is calculated
from the baudrate and targets to abort the transfer after approx.
20 bytes of 95 byte long transfer.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Some time ago a new shim for nRF UARTE was added (uart_nrfx_uarte2.c)
which used nrfx_uarte.c driver underneath. It was supposed to support
nrf54x platforms. However, later on legacy driver (uart_nrfx_uarte.c)
was extended to support nrf54x platforms and it takes less code size,
has better performance and more features. Shim uart_nrfx_uarte2 will
no longer be supported. As new shim is the default and there is a
Kconfig to pick the legacy shim (CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y)
it cannot be deprecated in the normal way. Additional Kconfig option
is created (DEPRECATED_UART_NRFX_UARTE_LEGACY_SHIM) which is enabled
if CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n and it selects DEPRECATED.
A warning was also added to the CMakeLists.txt.
Patch removes use CONFIG_UART_NRFX_UARTE_LEGACY_SHIM in tests.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add new target to the following tests:
- uart_elementary
- uart_async_api
- uart_mix_fifo_poll
- uart_pm
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Due to cm7 on RT1180 is secondary core, and dtcm have been used
as sram directly, so there is no need to define zephyr,dtcm node.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Enable device runtime PM for nrf54h20dk/nrf54h20/cpuapp where
fast UARTE (uart120) is tested.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
