In function wwdg_stm32_init, return value of clock_control_on
was not checked.
This is reported as an issue by coverity (CID 219600).
Fix this.
Fixes#33067
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In function gpio_stm32_enable_int, retiurn value of clock_control_on
was not checked.
This is reported as an issue by coverity (CID 219652).
Fix this.
Fixes#33035
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
RX/TX buffer depth are configurable parameters of DW_apb_i2c.
Change code from using fixed value I2C_DW_FIFO_DEPTH to using
register ic_comp_param_1 for RX/TX buffer depth.
Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>
Fix#32774
Bit position BIT(7) is 1000 0000 in binary which is actually the
bit positon 128. BIT(7) can be used as a mask, but we need to define
the position specifically as the integer 7.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Remove SPI_[0-8] and SPI_[0-8]_OP_MODES Kconfig symbols as no driver
uses them anymore. We also cleanup board and sample code to remove
use of these symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add MCGOUTCLK define to kinetis_mcg.h to make it possible to
use \`<&mcg KINETIS_MCG_OUT_CLK>\` in device tree.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Serial Wire JTAG configuration option is made available
under condition that SPI_3 was not enabled on SOC_STM32F103XE.
Besides being obsolete there are various other potential conflicts
with other periphals, and it is not possible to explicit them all.
To make it more coherent remove such condition, assume that user
needs to take care of such pin conflict and express SWJ as having
precedence over peripheral devices pin configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Lowest power consumption can be achieved when uarte peripheral
is disabled when not used. In low power mode, need for both
directions is tracked and if both are no in use peripheral is
disabled. TX disabling is instant but RX requires flushing RX
fifo because data in hardware fifo is lost when peripheral is
re-enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Refactored driver to prepare for low power extension. Functional
change is limited to handling of RX_DISABLED event which is now
generated from RXTO interrupt context after RX is stopped. Previously,
RX was not stopped after the transfer.
Rx flushing function contains hardware limitation workaround.
Workaround is applied only if flushed data is not discarded.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Some modems, under some conditions, have a tendency to get stuck without
a connection due to cached state. We have observed this on some Simcom
LTE modems after large cellular outages. The modems are unable to escape
their cached state for some reason unless they're factory reset (or a
cache clearence is forced in some other way).
This commit allows for the modem to be factory reset at each boot. This
minimizes dependencies on external state by ensuring each power-up is as
similar as possible.
Signed-off-by: Benjamin Lindqvist <benjamin.lindqvist@endian.se>
Current DW I2C driver uses 32 bit access for some registers and
16 bit access for others. So if DW I2C IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16
and 32 bit mix.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
As this header declares a function that uses a cube defined structure
as argument, it should include the matching header.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add SMP support.
Note: there is still limitation that we rely on NUM CPUs.
And all cpus must be from 0,1,2 and ....
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There was an error in the ordering of the parameters in the
DEVICE_DT_DEFINE for the native POSIX counter. This made a project
using a counter built for native posix not being able to compile.
This commit switches places for ctr_init and device_pm_control_nop.
Signed-off-by: Tofik Sonono <tofik@sonono.me>
Currently there is no way to distinguish between a caller
explicitly asking for a semaphore with a limit that
happens to be `UINT_MAX` and a semaphore that just
has a limit "as large as possible".
Add `K_SEM_MAX_LIMIT`, currently defined to `UINT_MAX`, and akin
to `K_FOREVER` versus just passing some very large wait time.
In addition, the `k_sem_*` APIs were type-confused, where
the internal data structure was `uint32_t`, but the APIs took
and returned `unsigned int`. This changes the underlying data
structure to also use `unsigned int`, as changing the APIs
would be a (potentially) breaking change.
These changes are backwards-compatible, but it is strongly suggested
to take a quick scan for `k_sem_init` and `K_SEM_DEFINE` calls with
`UINT_MAX` (or `UINT32_MAX`) and replace them with `K_SEM_MAX_LIMIT`
where appropriate.
Signed-off-by: James Harris <james.harris@intel.com>
Added CLOCK_CONTROL_NRF_FORCE_ALT dependency to some options which
are not valid when clock is controlled by out-of-tree driver.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Modified CLOCK_CONTROL_NRF_ACCURACY to represent integer value of
LF clock accuracy.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The shim layer could in some circumstances not be properly
configured which would result in an unbound radio interrupt
handler.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Add a name to the h4 rx thread.
It's useful to put a name on each thread for debugging, e.g., with the
shell's kernel threads command.
Signed-off-by: Pete Skeggs <peter.skeggs@nordicsemi.no>
Zero initialize the ch_handle in dma_pl330_configure().
The memset in dma_pl330_config_channel()is incorrect,
as the ch_handle is already populated with valid values and
the dma_pl330_config_channel() is overwriting with zeros.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
AArch64 has support for PSCI. This is especially useful for SMP because
PSCI is used to power on the secordary cores.
When the PSCI driver was introduced in Zephyr it was designed to rely on
a very PSCI-centric subsystem / interface.
There are two kinds of problems with this choice:
1. PSCI is only defined for the non-secure world and it is designed to
boot CPU cores into non-secure state (that means that PSCI is only
supposed to work if Zephyr is running in non-secure state)
2. There can be other ways or standards used to start / stop a core
different from PSCI
This patch is trying to fix the original wrong assumption by making the
interface / subsystem a generic one, called 'pm_cpu_ops', and using PSCI
only as an actual driver that is a user of this new interface /
subsystem.
For now the new subsystem is only exposing two methods: cpu_on and
cpu_off, others will probably follow according to the needs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
There is a hardcoded macro in Winc1500 HAL SPI driver
that would prevent the driver from working.
This macro is now defined only based on KConfig entry.
This KConfig entry is by default not set.
To enable, set "CONFIG_WINC1500_DRV_USE_OLD_SW=y"
in proj.conf or board.conf
Signed-off-by: Raja D. Singh <rdsingh@iotwizards.com>
Replace legacy API with new API. Note that this driver uses the
schedule, not reschedule, API, since triggers for delay never overlap.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Now that pinmux driver holds a table of GPIO device pointers,
use gpio device as the single source of trust for gpio_base
and remove use of port_base and related code.
This way, gpio_stm32_configure could directly take gpio device
pointer as argument.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use new gpio_stm32_clock_request function for GPIO clocks control.
To do this a new table of GPIO devices is set up at build time.
It is then used to populate targeted device when calling
gpio_stm32_clock_request.
Clean up remaining clock handling related code in the file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As a preparation for GPIO ports clocks power management,
add a dedicated central function fog GPIO ports clock toggling.
This function is made accessible to other users (pinmux).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On L4/L5 device, GPIO port G benefits from a dedicated supply
rail that should be enabled independently.
Review the code around this:
-Compile only when port G is enabled
-Assume that PWR clock is ON, as it is enabled as part of clock init
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The DMA module the i2s_sam_ssc relies on cannot change during the
runtime. Store pointer to dev_dma in flash, not in RAM. The new
implementation saves 40 bytes of flash and 32 bytes of RAM.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Either get priority from devicetree (liteeth) or remove Kconfig symbols
that aren't used anywhere for IRQ priority (gecko, stm32_hal).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Looking at the data sheet for the npcx section 4.15.5 CR_UART Core
Registers, the UICTRL register that is used in the npcx poll
functions is invalid when running in FIFO mode. Instead, calls to
uart_npcx_poll_in and uart_npcx_poll_out should be redirected to
their respective FIFO read/fill functions (when using interrupts).
Changes:
- When calling uart_poll_in: forward the request to uart_fifo_read.
- When calling uart_poll_out: loop until uart_fifo_fill returns
non-0 (we wrote 1 byte).
Signed-off-by: Yuval Peress <peress@chromium.org>
Simple reorg of the function declarations. This change moves
the interrupt driven functions declared at the bottom of the
uart_npcx.c file to the top, clustered under the same ifdef.
Signed-off-by: Yuval Peress <peress@chromium.org>
All dma drivers are devicetree based now so we can remove the last
bits of Kconfig associated with the old driver style.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We can utilize the devicetree macros to determine which instances to
enable. This will allow us to phase out the per instance Kconfig
symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Nothing sets the op mode to anything but master. For now default the
mode to master-only and we can determine a devicetree property in the
future if we need to support other configurations.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace Kconfig symbols SPI_DW_PORT_n_INTERRUPT_SINGLE_LINE with just
seeing how many IRQs are defined in the devicetree to determine single
or multiline interrupt support.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SoC that utilized the clock support isn't supported in Zephyr
anymore and there are no users of this code. Remove it for now as it
should get converted to utilize devicetree if needed in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace device_get_binding with DEVICE_DT_GET for getting access
to the io-channels/adc controller device.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace device_get_binding with DEVICE_DT_GET for getting access
to the io-channels/adc controller device.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace device_get_binding with DEVICE_DT_GET for getting access
to the io-channels/adc controller device.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If next_timeout() returns INT_MAX and pass it to
z_clock_set_timeout(), and machine goes to freeze or slow down.
Bad scenario as follows:
- If an argument int32_t ticks is set large value 0xffffffff,
ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);
replaces it into MAX_TICKS.
- uint32_t cyc will be set near by 0xffffffff
(this is 0xfffd7280 in 100 ticks per second).
- Add adjustment to cyc, adjustment max value is MAX_CYC.
(cyc = 0xffff14fd)
- Over 0x80000000 value of uint32_t is considered as negative
value of int32_t.
if ((int32_t)(cyc + last_count - now) < MIN_DELAY)
This condition is always true.
- Because cyc += CYC_PER_TICK will get overflow, driver sets mtimecmp
near value of current mtime.
(cyc = 0x00007fc0)
- Next timer interrupt will happen soon after return from interrupt
handler.
- By repeating these events, machine cannot go to next instruction,
and it's going to freeze or slow down.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Conver the NIOS-II mSGDMA driver to be devicetree based. Add node for
dma controller into nios2f.dtsi.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When running the tests of the async api of uart
on nucleo-l4r5zi we get MPU fault.
The reason is ordering initialization. The uart and dma
drivers are initialized PRE_KERNEL_1 while dmamux is
initialized POST_KERNEL.
Thus, the function device_get_binding fails since the
dmamux device is not ready to be used.
Fixes: #32715.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Convert driver and users of pinmux on mcux lpc platforms to getting
basic port info from devicetree (register address, label)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Deprecate the scl-pin and sda-pin properties in the devicetree.
Provide new scl-gpios and sda-gpios properties instead.
This lets the user specify SCL and SDA like this:
&i2c0 {
scl-gpios = <&gpio0 1 0>;
sda-gpios = <&gpio1 4 0>;
};
Instead of having to use:
&i2c0 {
scl-pin = <1>;
sda-pin = <36>;
};
Provide error checking and understandable error messages for invalid
configurations.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The current code is assuming that the SMC/HVC helpers can only be used
by the PSCI driver. This is wrong because a mechanism to call into the
secure monitor should be made available regardless of using PSCI or not.
For example several SoCs relies on SMC calls to read/write e-fuses,
retrieve the chip ID, control power domains, etc...
This patch introduces a new CONFIG_HAS_ARM_SMCCC symbol to enable the
SMC/HVC helpers support and export that to drivers that require it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Convert ism330dhcx INT_PIN attribute from Kconfigs to Device
Tree binding properties. Here int-pin has been defined as
enum with two possible values: 1 and 2.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Convert ism330dhcx accel and gyro odr attributes from Kconfigs to Device
Tree binding properties.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Converts ism330dhcx accel and gyro range attributes from Kconfigs to
Device Tree binding properties.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
SX1272 chip is very similar to the already supported SX1276;
unfortunately, Semtech provides a completely separate driver
for this one. This commit marks an attempt to avoid code
duplication by means of some not-very-pretty ifdefery.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
The default shell configuration has heavy flash and memory requirements,
requiring project maintainers to set many configuration options to "n"
to keep flash and memory requirements within reason.
This adds a new configuration option, CONFIG_SHELL_MINIMAL, which will
disable flash and memory heavy options by default, and allow project
maintainers to select/imply only the options they want.
On a quick test from an ARM board I'm working on, enabling this option
cut flash space requirements by ~8 KB, and memory requirements by ~1 KB.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
There is no longer a mem_block pointer in the stream struct so the
assert NULL check isn't relevant anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move dmamux_stm32_channels struct from device data to device
configuration and initialize the dmamux channel - dma channel
assignment during build time,
as this association is hardwired in all known series.
The information is taken from dma_offset and dma_requests device tree
properties. The current implementation is valid for series with either
a single or two dma peripherals and a single dmamux peripheral.
Both dmas can independently enabled.
As the driver uses multi-instance DT_INST_DEFINE, also macros for a
second dmamux are are added that should allow easier extension to a
second dmamux instance.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use timeout mechanism instead of unbounded loop during enabling ITIM32
module which source clock is LFCLK (32KHz).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
mpu9250 is a single package that contains both an mpu6050 6-axis
motion sensor and an ak8963 magnetometer. The two parts have
separate i2c addresses, yet despite the common mpu6050 component,
it has a different value in the "WHOAMI" register -- 0x71 instead
of 0x68.
This adds the additional chip id value in order to enable the use
of mpu9250.
Signed-off-by: Adam Serbinski <adam@serbinski.com>
Qemu when running more than one processor has a known synchronization
bug where counter values read from the HPET (notionally a single
global device) can be seen going "backwards" when read from different
CPUs.
There was a pre-existing workaround in the ISR that knew about this,
but the problem can crop up anywhere the counter value is used. In
particular I caught it aliasing with the "max_ticks" computation in
z_clock_set_timeout(), where it would cause a rollover and the
resulting negative comparator value would result in no end of
hilarity.
Wrap all access to the counter register with a counter() inline that
(when the workaround is enabled) forces the result to be monotonic by
clamping it to a minimum of one more than the previously read value.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This also makes it into arch_printk_char_out() which gets linked
in place of the weak symbol version, meaning printk() is usable
as soon as the stack is set up.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The driver was reworked recently so that driver capabilites are
obtained at runtime. The function to obtain the capabilities was
called after L2 initialization though, which is invalid as L2
initialization code already depends on certain driver capabilites.
Move the capability initializer to an earliest possible stage
(i. e. just after the core driver is initialized) to fix the issue.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
The comments at the beginning of the file are not quite correct
and instructions regarding configuration are not necessary at all.
Also remove the redundant first line.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move the SPI and I2C bus I/O bits into their own files. This makes
this driver more similar to other sensor drivers.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Now that we have various convenience macros in drivers/spi.h and
device.h defined, we can resolve some longstanding TODO items in how
this driver gets a hold of the devices it depends on:
- get bus devices with DEVICE_DT_GET
- get SPI chip select information with SPI_CONFIG_DT_INST
The results are shorter on boilerplate, save RAM, and improve boot
time.
The same techniques could be reused by other device drivers.
These changes require that the SPI bus and GPIO (for device CS)
devices used to interface with the BME280 are defined in devicetree.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We will need this to be able to DEVICE_DT_GET() bus devices from
tests/drivers/build_all in an upcoming commit.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We will need this to be able to DEVICE_DT_GET() bus devices from
tests/drivers/build_all in an upcoming commit.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The PDP context might be active.
If that's the case, the AT+QIACT command returns an error.
It's then not possible to succeed at setting up the module.
Furthermore, we apply the logic described in the Quectel Documentation :
- If there is an issue 3 consecutive times on activating/deactivating
the context, we restart the module.
- If the AT+QIDEAT command returns an error, we restart the module.
This PR is bug-fix aimed.
We leave parameterization of context ID for future enhancement.
Signed-off-by: Thomas LE ROUX <thomas.leroux@smile.fr>
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The stm32 uart driver fails to build on certian platforms due to
changes introduced by:
commit 3c18bcbf77
Author: Francois Ramu <francois.ramu@st.com>
Date: Wed Jan 27 10:27:33 2021 +0100
drivers: serial: stm32 restore uart after lowpower
Fix this by adding some ifdef's around the code that is specific to the
given platforms that the code works on.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Current implementation of uart_npcx_irq_{tx,rx}_ready always returns
false if the respective interrupt enable bit is not set, which means
that the api cannot be used if the interrupts are temporarily disabled
for whatever reasons, breaking patterns such as [1].
Other uart drivers also seems to not have this check, this patch removes
it from the NPCX driver too.
[1] https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/console/uart_console.c#L549
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This will export the stm32_clock_control_init function
to restore the clocks after the low power modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rework the checks for INPSEL, INNSEL, and C0_OFFSET_BIT presence to
avoid warnings when -Wexpansion-to-defined is enabled.
The warning was enabled in c7bc6380bd.
Fixes#32475.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This fixes the logic in erase_sector() for clearing the previous
sector number. The logic was reversed, clearing bits it should not
clear and keeping previous bits of the sector number. In practice this
does not seem to have had any effect on the current functionality, but
it will start to matter later if e.g. flash interrupts are enabled.
Signed-off-by: Göran Weinholt <goran.weinholt@endian.se>
Modifications to incorporate latest write to new flash area
Modification to avoid writing garbage to new flash area when compactor
is called during init.
Modifications to allow erase at partition size instead of eeprom
pagesize.
Modifications to better separate rambuf usage from flash usage.
Corrected some errors in compactor
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This driver emulates a EEPROM device in flash.
Reworked implementation with modified flash layout.
The emulation represents the EEPROM in flash as a region that is a
direct map of the eeprom data followed by a region where changes to
the eeprom data is stored. Changes are written as address-data
combinations. The size of such a combination is determined by the
flash write block size and the size of the eeprom (required address
space), with a minimum of 4 byte.
The eeprom page needs to be a multiple of the flash page. Multiple
eeprom pages is also so supported and increases the number of writes
that can be performed.
The eeprom size, pagesize and the flash partition used for the eeprom
are defined in the dts. The flash partition should allow at least two
eeprom pages. For fast read access a rambuffer can be enabled for the
eeprom (by setting the option rambuf in the dts).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
CAN_SYNC_SEG and ts1 are in common units. Both need to be scaled by 1000
to calculate the sample point.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In the npcx i2c FIFO mechanism, the hardware will release SCL bus
immediately after the driver reads data from FIFO. That's why we need
to hold SCL bus before configuring the next transaction. Once it was
done, the driver release the bus for the next transaction.
But during the last transaction, the driver releases SCL first then
starts a STOP condition. At this moment, the SCL is pulled high by PU
resistance and driven to low for generating STOP condition later. This
additional clock might influence some i2c devices if they don't reset
their state machine after receiving STOP.
This CL fixes this issue by two steps:
1. Distinguish that it's the last read transaction with STOP condition?
2. If so, issue STOP condition before reading FIFO instead of holding
SCL bus. Then the hardware will generate it immediately after reading
FIFO.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The definition to check if timers have up to 6 channels was causing
warnings when -Wexpansion-to-defined was enabled.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The first uart instance was already devicetree based. To be consistent
convert the second instance to also be devicetree based.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
QDEC_NRFX shall depend on either HAS_HW_NRF_QDEC,
or HAS_HW_NRF_QDEC0, since in the nRF5340 Application
core definition we select HAS_HW_NRF_QDEC0 instead of
HAS_HW_NRF_QDEC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
While running certain peci command, observed when FW attempts
to read last byte (Response FCS), PECI host controller returned
“Read FIFO” empty. Since “Read FIFO” is empty FW didn’t read
the response FCS.
Due to this issue, FW getting corrupted response from the PECI
controller for all the subsequent PECI commands.
To address this issue, FW waits for “Read FIFO” filled up by
the PECI controller.
Signed-off-by: Diwakar C <diwakar.c@intel.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This fixes a missing bit in the registers description
which results to wrong FIFO ODR configuration
when trying to configure a FIFO ODR higher than 833Hz
Signed-off-by: Clotilde Sattler <clotilde.sattler@stimio.fr>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a follow-up to commit 9f56cc5531.
Add net/ in the inclusion of ieee802154_radio.h so that the file can
be successfully included.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
