Add an emulation controller which routes eSPI traffic to attached
emulators depending on the selected chip(mostly host).
This allows drivers for eSPI peripherals to be tested on systems
that don't have that peripheral attached, with the emulator handling
the eSPI traffic.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Currently, zefi.py takes host GCC OBJCOPY as
default. Fixing the script to use CMAKE_C_COMPILER
and CMAKE_OBJCOPY.
Fixes: #27047
Signed-off-by: Spoorthy Priya Yerabolu <spoorthy.priya.yerabolu@intel.com>
Currently configuration for STM32F746G Discovery board on reset-start
event is inherited from included files (OpenOCD stm32f7x.cfg), but
contrary to the inherited adapter speed on reset-init event, the speed
inherited for the reset-start event is only 2000 kHz, which is not
available, so a lower speed is picked up automatically generating the
following message several times when flashing the board:
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
That commit overrides that suboptimal speed for reset-start event and
sets it to the same speed as used by reset-init event, i.e. the maximum
speed (4000 kHz), so the noisy messages like the above one disappear.
The change also improves a bit the throughput when writing to the board.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
This change enables support for KSZ8794 DSA device on the ip_k66f
board. Each LAN port is defined as a DTS subnode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch adds Kconfig entries to nRF5340-DK description that
automatically configure RPMsg Service if it is enabled for the build.
Co-authored-by: Piotr Szkotak <piotr.szkotak@nordicsemi.no>
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
When using Slim Bootloader the UART configuration isn't quite the same
as with the UEFI BIOS. In particular, UART2 is hidden in PCIe and is
instead accessible using a fixed MMIO address. Interrupts are also not
supported for this UART currently.
The simplest way to create builds against this special BIOS/bootloader
setup seems to be to create a new board variant/definition which lets
us provide a custom device tree overlay as well a dedicated Kconfig
default configuration.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The bt-uart, uart-pipe and bt-mon-uart DT chosen values are all
Bluetooth specific. Since Bluetooth isn't supported on the ehl_crb
board currently just remove these.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This CL provided an example of how turns on the low-voltage level
detection feature in npcx series. It demonstrates enabling low-voltage
level detection of I2C1_0 SCL/SDA io-pads if the power rail of their PUs
is 1.8V.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The BBC micro:bit v2 is a mini-computer that has been
designed to make the coding fun and easy to learn.
The micro:bit v2 is completely programmable so you can
easily bring your ideas to life! From making games to
creating music and even controlling robots.
The micro:bit comes with neat hardware such as a 25 LED
display, buttons, in-built speakers, Bluetooth 5 & Mesh
connectivity and sensors for temperature, motion & light.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Upgrade board specification to use the VirtIO board.
Keeps FPU run-time support disabled since the RISC-V 64-bit FPU
support in kernel appears to be non-functional.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The CONFIG_FLOAT_HARD config previously enabled the C (compressed)
ISA extensions (CONFIG_COMPRESSED_ISA). This commit removes that
dependency.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Configure QSPI NOR support and MX25R6435F on disco_l475_iot1 board.
Set MX25R6435F as flash controller and arrange partitions to take
newlay available space into account.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Sets the device tree chosen node for instruction tightly coupled memory
(ITCM) on all i.MX RT boards. Leverages the common Cortex-M linker
section instead of the SoC-specific one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Previous Zephyr environment required the usage
of external ESP-IDF cloning as source of headers
and libraries. The latest implementation uses external
module as source.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.
Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Replace these with links to the actual documentation as needed, or
just remove them entirely. These are getting copy/pasted around and
I'm trying to avoid that happening in the future.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
* give user permission to gcov bss section
* expand the size of iccm and dccm to 1M
Signed-off-by: Jingru Wang <jingru@synopsys.com>
Only enable hardware stack protection by default on the NXP TWR-K18F
development board if userspace is not enabled.
The NXP KE1xF SoC has 8 MPU regions, which is insufficient for using HW
stack protection and userspace simultaneously.
Fixes bc9a498bdf.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adding acrn configurations specific to the platform
on which acrn boots zephyr, Only the EHL specifc
configurations for now. Keeping the HW clock frequency to
1900Mhz for EHL and using the new APIc timer driver.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
Document on how memory is mapped in different configurations starting
from the MCUboot partitioning of the flash. The given examples are for
TFM use cases and dual-core samples.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Updates lpcxpresso55s69 board's documentation with mailbox and multicore
setups. Explain how _cpu1 and _ns targets are used.
Also fixes TFM related documentation.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Merges cpu0 and cpu1 targets to a single image, named multicore.bin,
this image can be found in the build folder.
Documentation is to be updated in a later commit.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
PWM, as other peripherals should not be enabled as part of
default board configuration.
Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds the board definition files
needed to support the Arduino Nano BLE 33.
Tested: the following have been verified with
my logic analyzer.
* Serial peripherals (UART, I2C, SPI)
* USB
* RTC
Untested:
* PWM. In theory it should work but I don't
have a good enough logic analyzer to test this
* RTC's. The board doesn't have a backup battery.
The peripherals are enabled for modding another
battery in the device tree.
Signed-off-by: Jefferson Lee <jeffersonlee2000@gmail.com>
This commit adds supports for the nRF52840 based BLE Cell board from
Contextual Electronics. This board contains support for BG95 Modem,
BQ52895 charger, SD card etc and can be used as a PI Hat.
In this commit, this board supports UART, I2C, SPI, Modem. Support
for charger, SD card and other things will be added later.
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
This patch includes the rtc in the doc for the
nucleo_g474re and nucleo_g431rb boards
from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch enables the rtc so that the testcase
tests/drivers/counter/counter_basic_api
can run on this nucleo_g071rb board
also when running sanity check
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The --nrf-family argument has been unnnecessary since 6628a16
(" runners: nrfjprog: boilerplate and recover rework").
Remove a few stragglers that are still using it, to avoid it being
copy/pasted into other board definitions.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The following features: 'i2c' and 'netif:eth' are now used in the
ip_k66f board. Let's mark them in the "supported:" section of the
ip_k66f.yaml.
The latter one is necessary as a prerequisite to run some tests (like
e.g. netif:eth is necessary to run network related ones).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Support the ST STM32 Nucleo-64 development board with
STM32L433RC SoC.
Tested samples: hello_world, blinky and button.
Signed-off-by: Matija Tudan <mtudan@mobilisis.hr>
By default nrfjprog presumes the pin reset will be used, and helpfully
enables it regardless of whether CONFIG_GPIO_PINRESET is selected or
not. Stop it from doing this so the second button can be used for the
application as requested.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The SAME70-XPLD board comes with an EEPROM that holds the MAC address
to be used with its Ethernet interface. Enable that feature by
default, so the application doesn't have to.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The default behavior of the log reader is to dump the full device trace
buffer. But that can contain output from a previous run and the state
parser in twister can get confused. Add a "--no-history" argument that
emits only new log data, which corresponds more closely to the way a
hardware UART would work.
(Code change is just two lines, everything else is comments & docs)
Fixes#30979
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
For a while now, we've had two APIC drivers. The older was preserved
initially as the new (much smaller, "new style") code didn't have
support for Quark interrupt handling. But that's long dead now. Just
remove it.
Note that this migrates the one board using this driver (acrn) to
CONFIG_APIC_TIMER instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This change adds support for configurable interrupt capabilities
in the emulated GPIO controller via Devicetree bindings.
Fixes#26477
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
The NPCX SMB modules provides full support for a two-wire SMBus/I2C
synchronous serial interface. Each SMBus/I2C interface is a two-wire
serial interface that is compatible with both Intel SMBus and Philips
I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7
series.
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller) Please refer Section 4.7.2 in the datasheet. In order to
support it, this CL seperates the i2c driver into port and controller
drivers. The controller driver is in charge of i2c module operations
and internal state machine. The port driver is in charge of pin-mux
and connection between Zehpyr i2c api interface and controller driver.
All of modules have separate 32-byte transmit FIFO and 32-byte receive
FIFO buffers. These FIFO buffers reduce firmware overhead during long
SMBus transactions by allowing the Core to write or read more than one
data byte at a time to/from the SMB module.
The CL also includes:
— Add npcx i2c port/controller device tree declarations.
— Zephyr i2c api implementation.
— Add "i2c-0" aliases in npcx7m6fb.dts for i2c test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Documentation update with information on how to run twiter integration
testing on this board. Also elaborate the discussion of permissions
setup.
(Longer term, it would be better to include a udev example of how to
set permissions on those files rather than doing it manually, and to
include fuller instructions on how to build the needed SOF driver
instead of just priving a link to a github tree.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add script signing and flashing up_squared_adsp board. Can be used:
$ west flash \
<zephyr>/boards/xtensa/up_squared_adsp/tools/flash.sh
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The existing implementation of the adsplog.py script worked fine for
individual runs (e.g. when running specific code) but had no support
for detecting system reset events and thus could not be used for
monitoring applications like test automation. It also could not
handle the case where a rapid log burst would overflow the buffer
before being noticed at the client. Also, the protocol here was also
rife with opportunities for race conditions. Fix all that up via what
is mostly a rewrite of the script. The protocol itself hasn't
changed, just the handling.
Also includes some changes to the trace_out.c code on the device side.
These are required to get ordering correct to make race conditions
tractably handleable on the reader side.
Some of the specific cases that are managed:
* There is a 0.4s backoff when a reset is detected. Continuing to
poll the buffer has been observed to hang the device (I'm fairly
sure this is actually a hardware bug, reads aren't visible to the
DSP software).
* The "no magic number" case needs to be reserved for detecting system
reset.
* Slot data must be read BETWEEN two reads of the ID value to detect
the case where the slot gets clobbered while being read.
* The "currently being filled" slot needs to always have an ID value
that does not appear in sequence from the prior slot.
* We need to check the full history in the buffer at each poll to
detect resets, which opens up a race between the read of the "next
slot" (which is absent) and the full history retrieval (when it can
now be present!). Detect that.
* A null termination bug in the current output slot got fixed.
Broadly: this was a huge bear to make work. It sounds like this
should be a simple protocol, but it's not in practice.
Also: clean up the error reporting in the script so it can handle new
PCI IDs being added, and reports permissions failures on the required
sysfs file as a human-readable error.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Change-Id: I211817620db2130ffb275a5962a24bf90aad57e9
Co-authored-by: Kevin Townsend <kevin@ktownsend.com>
Signed-off-by: David Vincze <david.vincze@linaro.org>
Musca-S1 is a Cortex-M33 based SoC. It's similar to the
Musca-B1, but among other things the embedded flash has
been replaced with embedded MRAM (eMRAM) memory.
The Musca-S1 files have been created based on the Musca-B1
SoC and board files.
Add the Musca-S1 board to the list of allowed platforms
for the TF-M integration examples.
Change-Id: I4f517d28d0a5b8c4a3fc3fab73adb5519acfc3c2
Signed-off-by: David Vincze <david.vincze@linaro.org>
This branch adds support for the nucleo_f303k8 board.
The configuration is based on the nucleo_l011k4,
the f302r8 and the ST reference manual.
I had successfully tested the following sample code:
blinky
blink_led (uses TIM2_CH1 on PA0)
button
hello_world
Signed-off-by: Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
Convert drivers to use pinmux devicetree node to create pinmux device
object.
On intel S1000 we add 'label' as a required property and set it to
'PINMUX' to match CONFIG_PINMUX_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Apart from the previously added pins, nRF21540's GPIO interface includes
also MODE pin. This commit adds this pin to relevant devicetree.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
The FEM requires a dedicated SPI interface. This commit puts it on SPI3,
removing the arduino SPI support.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Depending whether doorbell or plain versions are enabled, it will set
the right flags to qemu.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit adds more information about the litex_vexrscv board
target, including references to related projects and instruction
about generating bitstream for the Digilent Arty A7-35T Board.
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
In newer OpenOCD version from Zephyr's SDK v0.12, there are some
changes in OpenOCD scripts: JTAG probe interface (AKA "adapter")
setup, see http://openocd.zylin.com/#/c/5784/
And so we need to change OpenOCD scripts accordingly to match
newer OpenOCD version from Zephyr's SDK v0.12.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
OpenOCD cofig command: ftdi_device_desc description provides the
USB device description (the iProduct string) of the adapter. And If not
specified, the device description is ignored during device selection.
In newer OpenOCD version from Zephyr's SDK v0.12, there are some
changes in OpenOCD scripts.
In file interface/ftdi/digilent-hs1.cfg, ftdi_device_desc will be set to
"Digilent Adept USB Device", while we get the iProduct string
"Digilent USB Device" from em_starterkit adapter. it's better not
specify it and only use the vid and pid of the adapter for selection.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
XIP (eXecute In Place) is a method of executing programs directly
from long term storage (i.e flash memory). It allows us to
avoid copying text it into RAM, saving writable memory for dynamic
data and not the static program code.
We don't have such non-volatile memory capable for executing in
place on HSDK so we load Zephyr image to DDR memory with debugger
each time.
Disable XIP option for HSDK as we don't need it.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
On introduction of a "simplified" HSDK configuration where we only
use 2 cores out of 4 (in assumption that it will be working much
more reliably) we excluded a bit too much of details from OpenOCD script.
In particular we stripped not-used cores from JTAG chain description
which made OpenOCD quite unhappy:
----------------------------->8----------------------------
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: arc-em.cpu2 tap/device found: 0x200c24b1 (mfg: 0x258 (ARC International), part: 0x00c2, ver: 0x2)
Warn : JTAG tap: arc-em.cpu2 UNEXPECTED: 0x200c24b1 (mfg: 0x258 (ARC International), part: 0x00c2, ver: 0x2)
Error: JTAG tap: arc-em.cpu2 expected 1 of 1: 0x200424b1 (mfg: 0x258 (ARC International), part: 0x0042, ver: 0x2)
Info : JTAG tap: arc-em.cpu1 tap/device found: 0x200824b1 (mfg: 0x258 (ARC International), part: 0x0082, ver: 0x2)
Warn : JTAG tap: arc-em.cpu1 UNEXPECTED: 0x200824b1 (mfg: 0x258 (ARC International), part: 0x0082, ver: 0x2)
Error: JTAG tap: arc-em.cpu1 expected 1 of 1: 0x200024b1 (mfg: 0x258 (ARC International), part: 0x0002, ver: 0x2)
Info : JTAG tap: auto0.tap tap/device found: 0x200424b1 (mfg: 0x258 (ARC International), part: 0x0042, ver: 0x2)
Info : JTAG tap: auto1.tap tap/device found: 0x200024b1 (mfg: 0x258 (ARC International), part: 0x0002, ver: 0x2)
Error: Trying to use configured scan chain anyway...
----------------------------->8----------------------------
That lead us to the situation when the target cores were programmed
in a wrong way effectively failing all tests. Fixing it now.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
During review of ARC port of OpenOCD some changes were requested
in particular:
1. L2 cache (SLC in ARC parlance) semantics, see
http://openocd.zylin.com/#/c/5688/
2. JTAG probe interface (AKA "adapter") setup, see
http://openocd.zylin.com/#/c/5784/
And so we need to change OpenOCD scripts accordingly to match
newer OpenOCD version from Zephyr's SDK v0.12.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
There are three groups of sensors on this board, each of which
requires a different I2C bus configuration and a different power
supply. Currently only the CCS811 is supported.
Change the board configuration to pull the necessary information about
the CCS811 supply switch from devicetree, and to supply power based on
whether the device is enabled in devicetree (rather than whether a
driver is selected). The implementation is designed to support
additional supply switches (there are at least six on the board, most
of which are dedicated).
Also document the I2C configuration necessary for the other sensors.
There is currently no way to select alternative configurations without
editing the devicetree binding, but at least they're available for use
in overlays.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This reverts commit 7492841dd1.
Enabling CONFIG_INTEL_VTD_ICTL on UP Squared board results
in tests and apps hanging. So revert this for now.
Relates to #30574
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Enable spi1 interface that connects to STM module SPBTLE-RFTR on the
stm32l562e_dk board.
Tested the configuration with st_ble_sensor sample + ST BLE Sensor
app on Android phone.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
Defines partitions that can be used by mcuboot on nucleo_h743zi board.
Please note that mcuboot is not yet supported on stm32 h7 family as the
write-block-size is greater than 8.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
In native_posix and nrf52_bsim add the cpu_hold() function,
which can be used to emulate the time it takes for code
to execute.
It is very similar to arch_busy_wait(), but while
arch_busy_wait() returns when the requested time has passed,
cpu_hold() ensures that the time passes in the callers
context independently of how much time may pass in some
other context.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
The timer update was not triggering an immediate update of
the top HW models timer,
which meant a call to k_busy_wait() may have waited for a much
longer time than requested (up to 1 OS tick).
=> Fix it.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
for the signing procedures for boards an521, nrf5340, nrf9160,
nucleo_l552ze_q, and musca_b1.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
There is a GPIO driver for use with arty so enable the GPIO feature in
the board yaml to get some testing of it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the documentation of nRF5340 to stress that
TF-M is the default solution for building the Secure
image.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Extend the nRF5340 board's CMakeLists.txt file to
support building TF-M without BL2 for nRF5340. The
result of the build is a single merged-hex containing
TF-M (SPE) and Zephyr (NSPE).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Re-adjust the available RAM advertized by the nRF5340 DK
and PDK .yml files (Application core, Non-Secure version
of the board).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Modify the default partitioning of the Application core
SRAM, for Secure and Non-Secure domain, to accommodate
the default build configuration of TF-M. The RAM TF-M
uses should fit into the sram0_secure. The partitioning
should match what TF-M is allocating to secure and non-
secure domain.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When building with TF-M support (for non-secure Zephyr
applications) default to build TF-M without BL2 support.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Enable building with TF-M by default on nRF5340 DK Application
core (cpuapp) when building for the non-secure version of the
board.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Rework the runner to improve various issues.
Every board.cmake file for an nRF SoC target is repeating boilerplate
needed for the nrfjprog runner's --nrf-family argument. The
information we need to decide the --nrf-family is already available in
Kconfig, so just get it from there instead. Keep the --nrf-family
argument around for compatibility, though.
This cuts boilerplate burden for board maintainers.
We also need to revisit how this runner handles recovery to fix it
in nRF53 and keep things consistent everywhere else.
To cleanly handle additional readback protection features in nRF53,
add a --recover option that does an 'nrfjprog --recover' before
flashing. Keep the behavior consistent across SoCs by supporting it on
those too. Because this is expected to be a bit tricky for users to
understand, check if a --recover is needed if the 'nrfjprog --program'
fails because of protection, and tell the user how to fix it.
Finally, instead of performing a separate 'nrfjprog --eraseall', just
give --chiperase to 'nrfjprog --program' process's arguments instead
of --sectorerase. This is cleaner, resulting in fewer subprocesses and
avoiding an extra chip reset.
Having a separate 'west flash --recover' option doubles the number of
test cases if we want to keep exhaustively enumerating them. That
doesn't feel worthwhile, so update the test cases by picking a
representative subset of the possibilities. Each test now has enough
state that it's worth wrapping it up in a named tuple for readability.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Defines partitions that can be used by mcuboot on nucleo_h743zi board.
Please note that mcuboot is not yet supported on stm32 h7 family as the
write-block-size is greater than 8.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
nsim_hs_smp has 2 cores, and CONFIG_MP_NUM_CPUS defalut value is 2.
But some tests will have extra config: CONFIG_MP_NUM_CPUS=1, so we
need to launch cores according CONFIG_MP_NUM_CPUS, not using a fix
number 2.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Instrs_per_pass option specify the number of instructions excuted
before simulator switches operations. the default value is 512. If we
specify a small value for it the debugger's overhead will increase
significantly for simulation because of the time taken to rapidly
switch operations. And the overhead will cause some time critical
task failure.
Restore instrs_per_pass value from 10 to default 512, we will have a
good sanitycheck result for nsim_hs_smp.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
The SAM4E/S SoC have a ROM bootloader named SAM-BA. Add bossac
to the board west runner list. This requires Zephyr SDK 0.12.0.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This enables the LiteX clock control driver for litex_vexriscv platform.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
SRAM base address and size are currently hardcoded in the defconfig.
This is wrong because symbols like KERNEL_RAM_SIZE and KERNEL_VM_BASE
are not currently being set. Fix this by adding the correct DTS entry.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Set building TFM with MCUboot. Set the build configuration to
profile_medium, we need smaller TFM images to fit into flash.
Build MCUboot, TFM, sign it, sign Zephyr NS image and merge all the
images. Also change the other configuration, BL2=OFF, to merge as a
single image.
Update documentation on how to flash the board.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Create a special configuration when BL2=OFF is set. DTS partitioning is
used for MCUboot, but does not match TFM's flash_layout.h configuration
when BL2=OFF, DTS matches when BL2=ON.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Refactor lpcxpresso55s69's partitions to match TFM's flash_layout.h
configuration. This matches TFM with MCUboot configuration.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
I don't have much explanation for this change except that
I can't program soc on these boards with this option being set.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Similar to what was done for other h7 based boards,
use 'connect_assert_srst' and fix init routine.
Fixes#29732
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Resource sharing between m7 and m4 core was a bit abusive
as the whole SERIAL ports where disabled on m4 core.
Since it is possible to use a finer grain resource sharing and
having no serial node configured could lead to compilation issue
in some samples assign usart8 to m4 target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On these 3 stm32h7 based boards, 'connect_assert_srst' should
be used in order to be able to program after board unplug/plug.
Problem is that 'connect_assert_srst' prevents gdb-attach procedure
to complete which now requires 'reset halt' to be performed before
hand.
Fix this by forcing 'reset halt' by introducing a new init routine.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Since this board is fully supported on openocd,
let's use openocd to comply with other boards and
remove the dependency on stm32cubeprogrammer.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some pins on the arduino header and on the mikrobus header were wrong.
These are now corrected. They are the same on the lpcxpresso55s28
board.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
On stm32mp157c_dk2, the pin mapped on arduino connector pin A3
could not be used as GPIO.
As a consequence, pin "irq-gpio" from x_nucleo_iks01a3 shield
should not be used.
Use board overlay to remove it from shield definition.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
According to boards schematics, user button is pulled down by
external resistor when not pressed and pushing the button sets
it to high.
Fixes#30224
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a note in the documentation regarding the required
nRF Command Line Tools for properly working with the
nRF5340 DK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The current SAM4S define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current SAM4E define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The bug on TFM that prevented to enable MPU on NS side is
fixed on TFM current version.
MPU can now be safely enabled on NS target.
Fixes: #27809
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Discussion while adding the blackpill_f401ce board definition brought
up a few issues with the blackpill_f411ce board definition, which are
addressed in this commit:
* doc/index.rst had a typo
* support/openocd.cfg was incorrectly using the f4discovery profile,
which was fixed by using a custom profile for the SoC instead
* removed SoC from blackpill_f411ce.dts compatible line
* added support for jlink flash option
Signed-off-by: Kalyan Sriram <coder.kalyan@gmail.com>
Duplicates the existing blackpill_f411ce board definition for the
blackpill_f401ce board (WeAct Blackpill V3.0), which has identical specs
except for 84MHz clock (instead of 100Mhz) and 96K SRAM (instead of
128K).
Signed-off-by: Kalyan Sriram <coder.kalyan@gmail.com>
Update nrf21540 DTS to support FEM configuration and update other pins
according to te board datasheet
Signed-off-by: Jakub Pegza <Jakub.Pegza@nordicsemi.no>
The gpio port of D4 on the arduino header was incorrect and is now
corrected to PF_14.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
I have experienced some problems when flashing this board using OpenOCD.
Adding `connect_assert_srst` forces reset assertion before any
connection atempt (`srst_nogate` is required).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add i2c1 interface for stm32l552xx and stm32l562xx microcontrollers
and enable i2c1 that connects to lsm6dso sensor module on the
stm32l562e_dk board.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
Fix typos, inconsistent naming and formatting issues.
Also setting CONFIG_NFCT_PINS_AS_GPIOS=y because NFC is not used.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add Kconfig options that will be used by the module
to call the function with the desired parameters.
Refactor the tfm_integration samples and
the supported boards.
Update west.yml to bring in Cmake changes that use the new KConfigs.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
GR716A microcontroller evaluation board with features an 80-pin
mezzanine connector. Also supports simulating with TSIM3.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This board configuration is compatible with
- GRLIB GPL FPGA template designs
- TSIM3 LEON3 eval
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This board configuration can be used out-of-the-box with SPARC QEMU
distributed with Zephyr SDK v0.11.2.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Support for the NUCLEO-L031K6 development board with STM32L031K6 SoC.
Although the SoC only contains 32k flash and 8K RAM, it has been tested
on a number of samples and has worked as expected.
Signed-off-by: Steven Daglish <s.c.daglish@gmail.com>
Fixes: #28462
This commit allows shields to be defined in other BOARD_ROOTs, either
using `-DBOARD_ROOT=<path>` or a Zephyr module defined BOARD_ROOT.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This is done to facilitate multi image build systems
where child images could be associated with a different
core than the parent image.
In such situations, the name of the board associated with
the core of the child image must be known.
Boards for the 'CPUNET' domain is already in place.
This commit adds the boards for the 'CPUAPP' domain.
These would be needed if the parent image is build in the
'CPUNET' domain, and the child image is in the 'CPUAPP'
domain.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
For the application core, the `--device` parameter specifies only
the generic `cortex-m33`, so it is impossible for the debugger to
flash the target.
For the network core, the `--device` parameter is not present at all,
so it is even impossible to run the `debug` command.
This commit fixes the above issues by specifying the proper devices.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update nsim board documentation:
* add info about run on HW (HAPS)
* update info about dependencies in case of single / multi core
runs in simulation and run on HW
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
ARC nSIM boards (starting with nsim_ prefix) allow to run
Zephyr in simulator and on real hardware.
Allow to run Zephyr on HW by enabling mdb-hw runner.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
mdb runner is quite special as it can be used to run Zephyr on
both simulator (nSIM) and real hardware.
However it is really misleading as same command (west flash)
will run Zephyr in simulation for one board and try to run it
on HW for another board. Things are getting worse for boards
supporting both runs in simulation and on real hardware.
Let's split mdb runner for mdb-hw (for runs on HW) and mdb-nsim
(for runs in simulation) runners.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Move i2c to defconfig
Add documentation
Improve dts
Remove unnecessary option and only use the default ones.
Provide a default Active state directly in the device tree
Fix copyright
Signed-off-by: Stephane Dorre <stephane.dorre@gmail.com>
Disable setting CONFIG_SOC_FAMILY_NRF manually
Limit SPI frequency to 8MHz
configure new st7789v in device tree
Signed-off-by: Sergey Koziakov <dya.eshshmai@gmail.com>
Basic sample program that uses the one led and button from the Pinetime.
Led will turn on everytime the button is pushed.
Signed-off-by: Rafa Couto <caligari@treboada.net>
align kconfig option CONFIG_ARC_CUSTOM_INIT to
CONFIG_INIT_ARCH_HW_AT_BOOT. Remove unused CONFIG_ARC_CUSTOM_INIT in
kconfig.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
Add support for the BuyDisplay 3.5" TFT + touch shield based on ILI9488
controller and FT6236 touch.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Make driver generic for multiple ILI displays. The adopted strategy is
to share all driver code except register initialization, which has been
found to have some specific registers/values depending on the
controller.
The driver has been adjusted to support multiple compatibles.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
UART IP is clocked with 50MHz on HAPS by default. So switch
UART clock-frequency from 100MHz to 50MHz for nsim_* boards
so the binaries can be run on HAPS as well.
This property is dummy in case run in simulator (nSIM) so we
don't need to change anything in nSIM configuration files.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The nRF5340 (P)DK is equipped with the MX25R64 flash memory. Add a dts
node for that chip in the board definition as well as the missing QSPI
node in the nRF5340 SoC definition.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update the board image file in the nrf5340 documentation,
reflecting the fact that we now document the nRF5340 DK
instead of the PDK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Update the docs of nRF5340 board, to point to the
nRF5340 DK instead of the PDK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Convert handful of users of DEVICE_INIT to DEVICE_DEFINE or
SYS_DEVICE_DEFINE to allow deprecation of DEVICE_INIT.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update PWM pinctrl signal names of all non-F1 STM32 boards.
`pwm` variant is not available anymore on non-F1 series.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move the data/command GPIO from Arduino header 16 (D10), which collides
with Arduino SPI SS, to Arduino header 15 (D9).
Add commented example for specifying a reset GPIO on Arduino header 14
(D8).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
We deprecate nRF5340 PDK and add a note that
the board will be replaced by nRF5340 DK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Nordic Dev Kit board names were changed in Zephyr
v2.3 release, following the standard Board deprecation
policy. Two releases later we do not need to keep
references to the old names in the boards' documentation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This build target has all the low-memory options enabled for
memory management: a 4MB address space, 32-bit paging mode,
no KPTI, an empty page pool, and common page tables for
memory domains.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are set such that we have enough pages in the pool
for typical driver mappings and to instantiate two more
memory domains, which is what our tests require.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Replaces all existing variants of value clamping with the MIN and MAX
macros with the CLAMP macro.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
Add support for the recently introduced STM32CubeProgrammer runner.
Updated documentation to mention its availability as latest official
OpenOCD releases do not support H7 series.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There is no user USB port available on these boards.
Remove support and remove files when no more needed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enables the fat_fs sample on the mm_swiftio board by adding a
board-specific Kconfig overlay, and adding sdhc to the list of
board-supported features.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Following migration of pinctrl configuration from pinmux.c files
to device tree and deprecation of pinctrl defines, remove
pinmux.c files when possible.
Additionally remove the CMakeLists.txt files when it makes sense.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add Inventek es-WIFI modules shield. This shield exposes es-WIFI driver
using Arduino Uno R3 header by UART or SPI interfaces. It shows how
user can create their own overlay and expose es-WIFI driver.
The current Inventek's EVB doesn't have all pins necessary to control
the module by Arduino hearder. This shows how to wire to get ISM43xx
EVB working.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Update documention to refer to MEC152x specifications and
SPI image generator. MEC152x is the actual production SOC.
The only difference is the Boot-ROM loader SPI image layout.
Preserve the link to the old, MEC1501 SPI image generator.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Move STM32 based board USB pin configuration to device tree.
Exceptions:
* olimex_stm32_h407: Node not enabled and not documented.
Signal added in disabled node.
* L0/G4 based boards as signals are not available yet.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This qemu device is REALLY slow in icount mode. When I run it outside
of icount and watch the simulator advance the clock device in real
time, it looks to me like it expects the counter to be running at ~125
MHz. But it's set to a 12 MHz clock rate in its config, and trying to
use a 1000 Hz tick rate.
At those settings (and with the shift=3 argument to icount), I'm
measuring about 10k cycles to handle a minimal timer interrupt. But
if you do the math, that comes to 12k cycles per tick. The interrupt
takes as long as a tick! That would never work, except for the fact
that the timer driver on this device cheats and doesn't try to align
to ticks (basically ignoring all the lost time). And even that breaks
on the scheduler_api test (which does both tick and cycle math and
tries to compare them) when it's fixed to properly align itself.
One solution might be to set the clock rate to what qemu appears to
believe is the correct 125 MHz value. And that causes the test to
complete, but all tests now take ~10 minutes of real time because the
simulator is so slow!
So just make up some clock rates, it's a simulated platform after all.
I chose 5 MHz cycle time and 100 Hz tick rate, which on my device is
about half of "real" speed and very acceptable.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Refactors nxp i.mx, kinetis, and lpc board-level device trees to use
DT_SIZE_K and DT_SIZE_M macros to define external memory sizes. This is
self documenting and easier to read.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
I2S signals should now be configured using dt.
For nucleo_f411re, I2S pins were configured using SPI definitions
that pulled the same strings behind the scene as I2S would have done.
This being said, only CK and SD pins should be needed and were
documented, so I only left those.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This board has a multi-level power domain hierarchy where a sensor has
its own power control that is accessed through an external GPIO
peripheral that itself has a power control.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
In the flash partition definitions for ARM boards,
the link to the legacy partition macros does not
exist any more. The commit cleans up the partition
definition by removing this link.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
As a proof of concept, turn USB signals configuration to USB
for nucleo_wb5rg and disco_l475_iot1 boards.
This implicitly remove pull-up on _ID pin, which turn out to
have no side effect.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Sets the device tree chosen node for data tightly coupled memory (DTCM)
on i.mx rt boards that aren't already using DTCM as the chosen SRAM.
Leverages the common cortex-m linker section instead of the soc-specific
one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Removes the DATA_LOCATION Kconfig symbol from the i.mx rt soc series and
refactors corresponding boards to use a device tree chosen node instead.
The external SDRAM is chosen on all boards that can support it;
otherwise the internal DTCM is chosen.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
File names such as pcie_ep_bcm_iproc.c / pcie_ep_bcm_iproc_regs.h
seem unnecessarily long, same with CONFIG symbols' names.
Let's shorten them by replacing 'bcm_iproc' with simply 'iproc'.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
There are a few cases in which "altera" was used instead of "altr" as
the vendor prefix. Update DTS and bindings in those cases to use "altr"
Fixes#29373
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SPI NOR device on this board supports fastread, 2READ, DREAD,
4READ, and QREAD for read opcodes, but only PP and QPP for write
opcodes. Provide a clue to people trying to use 2READ with 2PP: it
won't work.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Deprecate the Musca-A board and SoC support to be removed in 2.6.0.
There are a number of issues with the Musca-A and there exists both the
Musca-B and Musca-S1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add chosen nodes for secure and non-secure RAM partitions
and update the common DTS to have a reserved-memory
node with all reserved RAM partitions
Signed-off-by: Alex Tsamakos <alex@actinius.com>
I2C1 pin configuration requires to enable remap on I2C1 pins.
Now this is transparent, it could be done easily, so enable
and configure pins for I2C1 on this board to enable arduino I2C.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move SPI pin configuration to device tree for all STM32 based
boards.
This should not bring any change in pin configuration.
Though, some adjuments have been made on following boards for
coherency:
* b_l4s5i_iot01a1: Removed "very-high-speed" on SPI3 MOSI pin.
Tested with no impact.
* black_f407zg_pro: SPI1 pins configured but not SPI1 node.
Removed pin config as not documented neither.
* sensortile_box: SPI2 pins configured but not SPI2 node.
Removed pin config as not documented neither.
* nucleo_g431rb/nucleo_g474re/nucleo_l476rg/nucleo_l4r5zi:
SPI2 and SPI3 pins were configured but missing.
Added since they were documented.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
-Add DMA channel details for the SPI DMA transfer
-Reserve HEAP_SPACE for DMA channel descriptors
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
There is a warning because of some pointer arithmetics in Grub,
that makes the build fail. The build works after disabling -Werror.
Signed-off-by: Maximilian Bachmann <m.bachmann@acontis.com>
Do not create bin file and remove all clutter. In this case we are
generating 1GB of data that will not be used.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a printk default hook that works in very early boot and doesn't
depend on the logging subsystem (which can still be used if desired,
of course). It speaks the same protocol, is somewhat smaller (MUCH
smaller if the app doesn't otherwise need the logging and ring buffer
dependencies), and more efficiently uses the output slot space by
doing line buffering and flushing only when needed.
Most importantly this one is MP-safe via both locking and cache
coherence management, and can work reliably when SMP is enabled.
(Note that "reliable" means that all output appears without corruption
-- simulateous logging by two CPUs can still interleave bytes, of
course).
Longer term, if we keep this protocol it would be good to unify the
two backends to reduce duplicated code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Significant rework of the Intel Audio DSP SoC/board layers. Includes
code from the following upstream commits:
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 25 16:34:36 2020 +0100
xtesna: adsp: use 50k ticks per sec for audio
Audio needs high resolution scheduling so schedule to nearest 20uS.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 24 13:59:01 2020 -0700
soc/xtensa/intel_adsp: Remove sof-config.h includes
This header isn't used any more, and in any case shouldn't be included
by SoC-layer Zephyr headers that need to be able to build without SOF.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat Jun 20 15:42:58 2020 -0700
soc/intel_adsp: Leave interrupts disabled at MP startup
This had some code that was pasted in from esp32 that was inexplicably
enabling interrupts when starting an auxiliary CPU. The original
intent was that the resulting key would be passed down to the OS, but
that's a legacy SMP mechanism and unused. What it actually did was
SET the resulting value in PS.INTLEVEL, enabling interrupts globally
before the CPU is ready to handle them.
Just remove. The system doesn't need to enable interrupts until the
entrance to the first user thread on this CPU, which will do it
automatically as part of the context switch.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 13:57:54 2020 +0300
dts: intel_cavs: Add required label
Add required label fixing build for CAVS15, 20, 25.
Fixes following errors:
...
devicetree error: 'label' is marked as required in 'properties:' in
bindings/interrupt-controller/intel,cavs-intc.yaml,
but does not appear in
...
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:19:56 2020 +0300
soc: cavs_v18: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:12:25 2020 +0300
soc: cavs_v20: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 14:59:23 2020 +0300
soc: cavs_v25: Remove dts_fixup fix build
Remove unused now dts_fixup and fix build with the latest code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:29:06 2020 +0300
soc: intel_adsp: Remove unused functions
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:53:58 2020 +0300
soc: intel_adsp: Clean up soc.h
Remove unused or duplicated definitions.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:02:23 2020 +0300
soc: intel_adsp: De-duplicate soc.h
Move soc.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:54:19 2020 +0300
soc: intel_adsp: Remove duplicated io.h
Move duplicated io.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:46 2020 +0300
cmake: Correct SOC_SERIES name for byt and bdw
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:02 2020 +0300
soc: intel_adsp: Build bootloader only for specific SOCs
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 11 13:46:25 2020 +0100
boards: xtensa: adsp: add byt and bdw boards WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 10 10:01:29 2020 -0700
soc/intel_adsp: Make the HDA timer the default always
The CAVS_TIMER was originally written because the CCOUNT values are
skewed between SMP CPUs, so it's the default when SMP=y. But really
it should be the default always, the 19.2 MHz timer is plenty fast
enough to be the Zephyr cycle timer, and it's rate is synchronized
across the whole system (including the host CPU), making it a better
choice for timing-sensitive applications.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:21:43 2020 +0300
soc: cavs_v25: Enable general samples build
Enables general samples build for SOC cavs_v25.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:13:53 2020 +0300
soc: cavs_v20: Enable general samples build
Enable general sample build.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:35:13 2020 +0300
soc: cavs_v18: Fix build general samples
Fix building general samples for CAVS18.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:22:40 2020 +0300
soc: intel_adsp: Add support for other SOCs
Support other SOCs in the "ready" message to the Host.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 13:25:39 2020 +0300
soc: intel_adsp: Move adsp.c to common SOC area
Move adsp.c to common and clean makefiles.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 17:18:18 2020 +0300
boards: intel_adsp: Remove dependency on SOF
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 14:29:44 2020 +0100
soc: xtensa: cavs: build now good for cavs20 + 25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 15:57:01 2020 +0300
soc: cavs_v15: Fix build for hello_world
Fix build for other then audio/sof targets.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:50:12 2020 +0300
sample: audio/sof: Remove old overlays
Removing old overlays used to switch logging backend.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 15:02:01 2020 +0300
soc: intel_adsp: Correct TEXT area
Correct HEADER_SPACE and put TEXT to:
(HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE + VECTOR_TBL_SIZE)
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:44:47 2020 +0300
soc: intel_adsp: Trivial syntax cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:41:07 2020 +0300
soc: intel_adsp: Fix bootloader script path
Make it possible to find linker script if build is done not inside
ZEPHYR_BASE.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 12:10:17 2020 +0100
soc: xtensa: cavs20/25: fix build with new headers - WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 13:35:38 2020 +0300
soc: intel_adsp: Fix include headers
Fixes include headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 10:38:50 2020 +0100
soc: xtensa: cav18: updated headers- WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Fri May 1 15:29:26 2020 -0700
soc/xtensa/intel_adsp: Clean up MP config logic
CONFIG_MP_NUM_CPUS is a platform value, indicating the number of CPUs
for which the Zephyr image is built. This is the value kernel and
device code should use to predicate questions like "is there more than
one CPU?"
CONFIG_SMP is an application tunable, controlling whether or not the
kernel schedules threads on CPUs other than the first one. This is
orthogonal to MP_NUM_CPUS: it's possible to build a "SMP" kernel on a
uniprocessor system or have a UP kernel on a MP system if the other
cores are used for non-thread application code.
CONFIG_SCHED_IPI_SUPPORTED is a platform flag telling an SMP kernel
whether or not it can synchronously signal other CPUs of scheduler
state changes. It should be inspected only inside the scheduler (or
other code that uses the API). This should be selected in kconfig by
soc layer code, or by a driver that implements the feature.
CONFIG_IPM_CAVS_IDC is a driver required to implement IPI on this
platform. This is what we should use as a predicate if we have
dependence on the IPM driver for a platform feature.
These were all being sort of borged together in code. Split them up
correctly, allowing the platform MP layer to be unit tested in the
absence of SMP (c.f. tests/kernel/mp), and SMP kernels with only one
CPU (which is pathlogical in practice, but also a very good unit test)
to be built.
Also removes some dead linker code for SMP-related sections that don't
exist in Zephyr.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:41:55 2020 +0100
soc: xtensa: bootloader - use linker script
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:26:18 2020 +0100
soc: xtensa: further fix headers - WIP
Simplify the directory structure, WIP for cavs20 and cavs25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 12:59:30 2020 +0300
soc: cavs_v15: Remove unneeded include
Remove include fixing build.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Jun 7 12:37:35 2020 +0100
soc:xtensa: adsp: remove sof specific code from soc headers
TODO: v1.8+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 23:19:37 2020 -0700
intel_adsp_*/doc: fix duplicate .rst labels
Quick fix purely to make the build green again.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 22:34:40 2020 -0700
samples/audio/sof: use OVERLAY_CONFIG to import apollolake_defconfig
This reverts commit 21f16b5b1d29fca83d1b62b1b75683b5a1bc2935 that
copied it here instead.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 5 12:34:48 2020 +0300
soc: intel_adsp: Move soc_mp to common
Moving soc_mp to common SOC area, it still needs fixes for taking
number of cores from Zephyr Kconfig, etc.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 16:05:06 2020 +0300
soc: intel_adsp: Move memory.h from lib/
For those files from SOF referencing platform/lib/memory.h we have
include.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 15:20:09 2020 +0300
soc: intel_adsp: Rename platform.h to soc.h
Rename to prevent including it from SOF.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:47:55 2020 +0300
soc: intel_adsp: Move headers
Move headers to more convenient place
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:21:51 2020 +0300
soc: intel_adsp: More SOC cleaning
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Mon Jun 1 15:31:34 2020 -0700
samples/audio/sof: import sof/src/arch/xtensa/ apollolake_defconfig
Import modules/audio/sof/src/arch/xtensa/configs/apollolake_defconfig
into prj.conf and new boards/up_squared_adsp.conf
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:07:40 2020 +0100
soc:xtensa: adsp: let SOF configure the DSP for audio
Let SOF do this for the moment.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:06:20 2020 +0100
soc: xtensa: cavs: remove headers similar to cavs15
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 15:58:38 2020 +0300
soc: intel_adsp: Move ipc header to common
Remove duplicated headers from CAVS to common SOC part
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 13:02:09 2020 +0300
soc: cavs_v15: Remove unneeded headers
Remove also from CAVS15.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 18:34:11 2020 +0300
Remove more headers
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:12:09 2020 +0100
soc: xtensa: remove cavs sod headers for drivers and trace.
Duplicate cavs15 headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:05:12 2020 +0100
samples: move sof dai, dma and clk configs to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 17:38:45 2020 +0300
soc: intel_adsp: Remove more duplicated headers
Remove more headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 2 15:50:03 2020 +0100
samples: sof: remove pm realted files.
Use the SOF versions.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 16:55:40 2020 +0300
WIP: Strip lib from include path
WIP, pushed for sync
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:44:33 2020 +0300
soc: intel_adsp: Remove more headers
Remove even more common headers
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:00:47 2020 +0300
soc: intel_adsp: Remove SOF headers
The headers would be used by audio/sof app directly from SOF module.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat May 30 11:01:26 2020 -0700
soc/intel_adsp: Alternative log reading script
This script speaks the same protocol and works with the same firmware,
but:
* Is a single file with no dependencies outside the python3 standard
library and can be run out-of-tree (i.e. with setups where the
firmware is not built on the device under test)
* Operates in "tail" mode, where it will continue polling for more
output, making it easier to watch a running process and acting more
like a conventional console device.
* Has no dependence on the diag_driver kernel module (it reads the DSP
SRAM memory directly from the BAR mapping in the PCI device)
* Is MUCH smaller than the existing tool.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 28 16:17:51 2020 +0300
Decrease HEP pool size to 192000
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:27:00 2020 +0100
soc: xtensa: cavs25: complete support for cavs25
Builds, not tested on qmeu due to missing SOF ROM (TODO)
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:24:26 2020 +0100
soc: xtensa: cavs20: complete cavs20 support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:22:13 2020 +0100
soc: xtensa: cavs18: complete boot support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:19:23 2020 +0100
soc: xtensa: cavs15: use cavs15 instead of apl as linker soc name
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:16:06 2020 +0100
TODO: samples: sof: work around missing trace symbols.
Disable local trace.
Needs trace updates finished before this can be removed.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:57:19 2020 +0100
dts: xtensa: rename apl to cavs15 DTS
This DTS is used by more than APL SOC. i.e. all CAVS15 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:52:20 2020 +0100
west: commands: sign: Add signing support for other CAVS targets
Sign for CAVS15, CAVS18, CAVS20 and CAVS25 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:50:07 2020 +0100
boards: xtensa: cavs: used Zephyr mask macro
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:49:46 2020 +0100
soc: xtensa: move code to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 26 11:40:36 2020 +0100
soc: xtensa: use SOF versions of clk
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:38:45 2020 +0300
soc: intel_adsp: Send FW ready for non SOF configuration
Configure windows and send FW ready when used without SOF, should be
loaded with fw_loader script.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:02:22 2020 +0300
soc: intel_adsp: Use SOF version of the file
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:47:27 2020 +0300
soc: intel_adsp: Clean up include headers
Remove SOF mentions from the SOC headers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:43:05 2020 +0300
soc: intel_adsp: Move SOF specific code to samples/audio/sof
Move SOF specific code to the SOF sample.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:39:42 2020 +0300
soc: intel_adsp: Use SOF module's version of mem_window.c
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:36:41 2020 +0300
soc: intel_adsp: Use exact copy from SOF module
Use SOF module verion of the clk.c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 14:03:35 2020 +0300
soc: xtensa: Add {SOC_FAMILY}/common/include path
Add ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include path if exist.
Fixes issues for xtensa SOCs.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:18:50 2020 +0100
soc: xtensa: cavs common: fix headers for build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:10:57 2020 +0100
soc: xtensa: adsp: add so_inthandlers.h for Intel platforms
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:08:26 2020 +0100
cmake: xtensa: select correct compiler per CAVS target.
TODO: what about XCC ?
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue May 19 14:59:26 2020 +0300
boards: up_squared_adsp: Move SOF configuration to samples
Move SOF-specific configuration to samples/audio/sof prj.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 15 15:29:50 2020 +0300
soc: intel_adsp: Move SOF code to modules/audio/sof
Move SOF dependent code out of SOC area.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 14 17:30:38 2020 +0300
Move task_main_start() to audio/sof sample
Start task_main_start() from main of audio/sof sample.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed May 13 15:37:20 2020 +0300
Rename up_xtreme_adsp to intel_adsp_cavs18
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Apr 27 14:12:59 2020 +0300
Add sample audio/sof for SOF initialization
Add dedicated sample where we put SOF specific initialization.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 18:49:36 2020 +0300
WIP: soc: cavs_v18: Cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:44:06 2020 +0300
soc: cavs_v15: Move soc init to common part
Moving SOC init to the right place.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:02:28 2020 +0300
soc: intel_adsp: Move common part to special dir
Moving common part to common/adsp.c
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 8 14:37:50 2020 +0300
boards: up_xtreme_adsp: Add initial up_xtreme_adsp board
Add initial board copying existing up_squared_adsp board and using
CAVS1.8 SOC family.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 7 15:30:51 2020 +0300
soc: intel_adsp: Generalize bootloader
Move bootloader to soc/xtensa/intel_adsp making it available for other
boards.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:31:00 2020 +0100
boards: xtensa: up_squared: Add support for all CAVS
Add boot support for all CAVS versions. TODO: needs to be made common
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:25:34 2020 +0100
soc: xtensa: intel_adsp: Manage cache for DMA descriptors
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 21:10:50 2020 +0100
soc: xtensa: adsp: use 24M567 clock
Use audio clock
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 10:04:01 2020 +0100
xtensa: soc: adsp: enable system agent
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:03:07 2020 +0100
soc: xtensa: intel_adsp: increase mem pool to 192k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:02:31 2020 +0100
soc: xtensa: intel_adsp: re-enable DMA trace
Buffer will be empty (as trace items sent to Zephyr LOG) but
logic is running.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 11:18:55 2020 +0100
soc: xtensa: intel: dont use uncache region yet.
Some code was still using this region. Use later.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 10:07:28 2020 +0100
soc: xtensa: intel_adsp: fix notifier init
Topology now loads.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:18:38 2020 +0100
boards: up2: Need to use sof config for bootloader
This will need uncoupled at some point. For testing today.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:16:38 2020 +0100
boards: up2: increase heap to 128k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:35:19 2020 +0300
boards: up_squared_adsp: Use bigger HEAP
Use HEAP from old demo.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 16:06:32 2020 +0100
soc: xtensa: intel_adsp: Fix config.h naming collisions
Rename sof version to sof-config.h
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:22:42 2020 +0300
Small cleanups
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 22:00:44 2020 +0300
tests: sof/audio: Test ll scheduler
Add more tests for scheduler.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 18:38:35 2020 +0300
tests: Add first schedule test
Add initial test for testing scheduling.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 29 13:36:23 2020 +0100
soc: xtensa: rmeove build warnings
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 18:04:33 2020 +0300
soc/intel_adsp: Register sof logging
Register sof logging for tracing
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 14:16:55 2020 +0300
boards: up_squared_adsp: Define HEAP_MEM_POOL_SIZE
Define HEAP_MEM_POOL_SIZE when SOF enabled.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 10:09:20 2020 +0300
tests: audio/sof: Add interrupt API for testing
Add initial interrupt API for testing.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 15:54:28 2020 +0100
soc: xtensa: adsp: Update linker script for SOF sections.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 11:20:01 2020 +0100
soc: xtensa: adsp: send SOF FW metadata as boot message
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 26 21:47:20 2020 +0100
soc: xtensa: adsp: re-enable all SOF IP init.
Do all SOF IP init.
TODO: ATOMCTL, WFI on LX6
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sat Apr 25 15:30:40 2020 +0100
soc: xtensa: irq: Make sure IPC IRQ is registered.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 20:56:09 2020 +0300
tests: sof: Enable console
Enable console for the test.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 17:57:22 2020 +0300
soc: cavs_v15: Fix XTENSA_KERNEL_CPU_PTR_SR
Use correct value for XTENSA_KERNEL_CPU_PTR_SR.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 14:48:31 2020 +0300
tests: audio/sof: Add tests for alloc API testing
Add initial tests for allocation API testing. Can be extended for
other later.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 17:49:32 2020 +0300
logging: Enable xtensa simulator backend for ADSP
Enable xtensa simulator backend for SOC_FAMILY_INTEL_ADSP.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 20:58:30 2020 +0100
soc: xtensa: add common cpu logic
Support for additional cores.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 10:11:07 2020 +0300
Update west.yaml to point to the latest repo
Update west.yaml
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:17:01 2020 +0100
soc: xtensa: cavs: Fix build for clk.c on cavs18+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:31 2020 +0100
soc: xtensa: cavs15: removed unused headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:09 2020 +0100
soc: xtensa: cavs25: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:52 2020 +0100
soc: xtensa: cavs20: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:09 2020 +0100
soc: xtensa: cavs18: Align with SOF headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 11:42:39 2020 +0100
west: sof: Updated to latest version.
Now builds, links and runs SOF code (but not to FW ready).
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 19 13:28:53 2020 +0100
xtensa: intel adsp: build in SOF symbols if CONFIG_SOF
Code now fully links against SOF. Needs to be run tested.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:19:28 2020 -0700
DO NOT MERGE: temporarily add thesoftproject as remote for sof module
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:33:40 2020 -0700
ipm: cavs_idc: use the IPC/IDC definitions in SoC
The SoC definitions have the necessary IPC/IDC bits so there is
no need to define them separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 14:30:20 2020 +0100
TODO: config: Use static config for SOF module.
TODO: needs to be generated as part of SOF kconfig
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri Apr 10 21:56:07 2020 +0100
HACK: Add SOF into build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:55:15 2020 +0100
west: modules: Add SOF audio module.
Add support for building SOF as a Zephyr module. This is the starting
point for add SOF audio into Zephyr. Currently builds but does not use
any symbols yet.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:48:48 2020 +0100
WIP soc: adsp-cavs15: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:43:44 2020 +0100
WIP soc: adsp-common: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:36:32 2020 +0000
WIP: soc: adsp-common: cache is common across all Intel ADSP platforms
De-duplicate soc.h cache definitions.
TODO: this needs done for other common functions.
TODO: need to fix include path
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:43 2020 -0700
WIP: soc: cavs25: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:12 2020 -0700
WIP: soc: cavs20: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:06:40 2020 -0700
WIP: soc: cavs18: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 12:37:17 2020 -0700
soc: intel_adsp: use main_entry.S in common for cavs_v15
The files are identical anyway.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:38:14 2020 -0700
soc: intel_adsp/cavs_v15: link common code
Let cavs_v15 link against the code compiled under common/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 13:08:28 2020 +0000
WIP: soc: common: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:37:32 2020 +0000
WIP soc: adsp-cavs15: build power down support
Build the power down support for CAVS1.5
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 12:40:17 2020 +0000
WIP: soc: cavs15: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:30:08 2020 +0000
soc: cavs15: Add missing SHIM registers.
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 9 15:43:01 2020 +0000
xtensa: intel_adsp/cavs_v15: fix usage of LP SRAM power gating
Remove LSPGCTL as it can cause confusion, use SHIM_LSPGCTL instead.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Feb 26 15:28:48 2020 +0000
boards: up_squared_adsp: Use local xtensa HAL instead of SDK HAL
SDK HAL is deprecated for Intel ADSP SoCs so fix and use local HAL
module.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 10:45:15 2020 -0700
soc: add Intel Audio DSP SoC family
This creates a SoC family for the audio DSPs on various
Intel CPUs. The intel_apl_adsp is being moved into
this family as well, since it is part of the CAVS v1.5
series of DSPs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:29:02 2020 -0700
soc: xtensa: add CMakeLists.txt
Add CMakeLists.txt under soc/xtensa so that CMakeLists.txt
inside each SoC directory will be included, similar to
what ARM and RISCV have.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:43 2020 -0700
Revert "boards: up_squared_adsp: Add flasher script"
This reverts commit 80f295a9dd.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:32 2020 -0700
Revert "boards: up_squared_adsp: Update logtool tool"
This reverts commit 7770d182c1.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:23 2020 -0700
Revert "soc: intel_adsp: Generalize bootloader"
This reverts commit d6a33ef467.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
soc: xtensa; intel: remove sof-config.h - SQUASH
No longer used.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
GPIO_AD_B0_01 is connected to the reset pin through a specific circuit.
This is a special mechanism of swiftio to check the download. Therefore,
it can't be default to the pinmux of spi3, and spi3 will be dynamically
configured in the application.
Signed-off-by: Frank Li <lgl88911@163.com>
Most DT bindings use reset-gpios name when there is a pin to reset whole
chip. Rename wifi-reset-gpios to reset-gpios to be more consistent
between various drivers. Additionally this prevents confusion, as
somebody might think that this pin resets only WiFi, which is not true.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Pass the compiler name and path to the TF-M post-build
script as an argument, so the TF-M build can work with
the Zephyr SDK as well (not only with the GNU ARM embedded
toolchain.)
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add the required documentation extensions for the nRF5340
and the nRF9160 DKs that explains how to build and run
Zephyr with TF-M as the Secure firmware image counterpart.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding support for TF-M in the Nordic nRF9160 DK.
Allow the TF-M integration samples to be built and
executed for nRF9160 DK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Update the TF-M post-build scripts in the relevant
ARM platforms in the wake of updating TF-M to the
latest upstream.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
TF-M related information in the relevant board definitions
needs to be updated in the wake of the new TF-M Build
system.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The only user of the I2C instances is the esp32 driver. Move the
Kconfig symbols down to the esp32 Kconfig for the instances it needs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enable HW stack protection by default in the board
definitions of ATMEL-based platforms.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Support for the NUCLEO-L011K4 development board with STM32L011K4 SoC.
Although the SoC only contains 16K flash and 2K RAM, it has been tested
on a number of samples and has worked as expected.
Signed-off-by: Steven Daglish <s.c.daglish@gmail.com>
Add support for the STM32L562E-DK Discovery board
(based on the nucleo_l552ze_q board).
Tested with hello_world, basic/blinky, basic/button.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
These need an initial compatible to be recognized as SPI devices.
Also fix a typo in the base include file, and ensure the overlays are
the same for all variants.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This makes the 72Mhz HFRCO drive the MCU HF clock, and only uses
the HFXO to drive the ethernet clock.
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
This defines the TRNG for EFM32GG11 and enables it for trng0
in the dts for the matching development kits.
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
This defines wdog0 and wdog1 for the EFM32GG11 MCU and enables wdog0
in the dts for the matching development kits.
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
Use the new DT facilities to configure ADC pinmux on all boards with
STM32 MCUs currently supporting the ADC.
Signed-off-by: Martin Jäger <martin@libre.solar>
If neither a random address nor a specific local address is in the
device tree, then use the MAC address from the device information page.
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
The Cypress cy8ckit_062_wifi_bt kit is splitted on two directories.
There is no reason to keep it separated. This squash M4 and M0 boards
as one board file.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add pinctrl-0 property for CAN nodes and remove pinmux.c.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martin Jäger <martin@libre.solar>
The WGM160P module combines the WF200 Wi-Fi transceiver with
an EFM32GG11 MCU
This code is based on the efm32gg_stk3701a board definitions
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
Use the new DT facilities to configure DAC pinmux on all STM32 nucleo
boards currently supporting the DAC.
Signed-off-by: Martin Jäger <martin@libre.solar>
The nrf52 bsim hw models now require some of these to
be defined. For this case we cannot implement these
as static inline functions as that would redefinitions
of the functions.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
