Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Even though possible to use external pull-up and open drain buffer,
prefer internal pull-up to reduce power consumption.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Added support for RNG for stm32l562e_dk board, and updated
the document.
Tested with sample entropy project.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
Added support for RNG for nucleo_l552ze_q board, and updated
the document.
Tested with sample entropy project.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
Add support for u-blox BMD-300-EVAL. Also includes BMD-301-EVAL
and BMD-350-EVAL. All share the nRF52832, and are functionally
equivalent to the nRF52dk_nrf52832 with the exception of not
having debug-in and the shield SWD header.
Note that header pin numbers noted in index.rst are shown with
respect to the pin 1 markings on the BMD-3xx-EVAL boards, and are
flipped from the nRF52dk_nrf52832.
Tested with blinky, button, and Bluetooth peripheral_hr
Corrected type in index.rst (should be nRF52dk_nrf52832, not ..810)
Signed-off-by: Bob Recny <bob.recny@u-blox.com>
The GPIO drivers are initialized in the POST_KERNEL level with the
default priority, so whether they're available at the time the sysinit
function requires them depends on how the linker orders the init
records. Since we can't set a priority relative to the default
priority, hard-code the maximum priority and hope it's good enough.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add dts files for the specific chip instances that are used on the
boards in prep of having pin data in devicetree. The pin data will
be specific to the given chip instance so we need to distinguish
unique chips for the same SoC as the pin mux will differ.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The low power states 0∕1∕2 are added to the stm32wb55rg
nucleo board, with default min residency values.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32wb55 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable MSI hardware auto calibration for this stm32l562
disco board. It depends on the STM_LSE clock.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l562e_dk board
with default min residency values.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l562 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch introduces the support of the LowPower Timer
for the STM32l562ze disco kit (sec. and non-sec. version)
LSE clock is selected as LPTIM clock source on this board.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l476rg
nucleo board, with default min residency values.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l476 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
As of today the build-only testing in upstream is enabled for
nsim_em and nsim_em7d_v22 which are very similar from the
compiler POW. The ARC HS, ARC Secure EM and SMP targets miss
any testing.
So adjust default testing for better coverage by enabling
build-only testing for nsim_hs, nsim_sem and nsim_hs_smp and drop
excessive testing for nsim_em7d_v22.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Enabling I2C support for Nucleo-F207zg in device tree.
This has been tested with mpu6050 sample application on I2C-1.
Documentation has been updated.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Before this fix the board init function were called too early, before
the gpio driver was initialized. Because of the the board controller
for the serial port was not enabled properly.
This commit fixes this issue.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
* Removed leading 0 from slot0_partition starting offset
* Fixed slot1_partition starting offset
This fixes the following warnings:
nucleo_g0b1re.dts.pre.tmp:1749.36-1752.5: Warning
(unit_address_format):
/soc/flash-controller@40022000/flash@8000000/partitions/
partition@0C000:unit name should not have leading 0s
warning: unit address and first address in 'reg' (0x3e000) don't match
for /soc/flash-controller@40022000/flash@8000000/partitions/
partition@31000
Signed-off-by: Raúl Sánchez Siles <rsanchezs@k-lagan.com>
Enabling DAC support for STM32 nucleo_f429zi in device tree.
Documentation has been updated.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Enabling SPI support for Nucleo-F207zg in device tree.
This has been tested with test_spi_loopback on SPI-1.
Documentation has been updated.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Configures the pinmux for the Arduino D9 pin to allow using it as a
gpio. This is needed by the adafruit_2_8_tft_touch_v2 shield for
cmd-data-gpios.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds Arduino header pin mappings to the mimxrt685_evk board to enable
using it with the adafruit_2_8_tft_touch_v2 shield and lvgl sample.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The fatal log now contains
- Trap type in human readable representation
- Integer registers visible to the program when trap was taken
- Special register values such as PC and PSR
- Backtrace with PC and SP
If CONFIG_EXTRA_EXCEPTION_INFO is enabled, then all the above is
logged. If not, only the special registers are logged.
The format is inspired by the GRMON debug monitor and TSIM simulator.
A quick guide on how to use the values is in fatal.c.
It now looks like this:
E: tt = 0x02, illegal_instruction
E:
E: INS LOCALS OUTS GLOBALS
E: 0: 00000000 f3900fc0 40007c50 00000000
E: 1: 00000000 40004bf0 40008d30 40008c00
E: 2: 00000000 40004bf4 40008000 00000003
E: 3: 40009158 00000000 40009000 00000002
E: 4: 40008fa8 40003c00 40008fa8 00000008
E: 5: 40009000 f3400fc0 00000000 00000080
E: 6: 4000a1f8 40000050 4000a190 00000000
E: 7: 40002308 00000000 40001fb8 000000c1
E:
E: psr: f30000c7 wim: 00000008 tbr: 40000020 y: 00000000
E: pc: 4000a1f4 npc: 4000a1f8
E:
E: pc sp
E: #0 4000a1f4 4000a190
E: #1 40002308 4000a1f8
E: #2 40003b24 4000a258
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This change is needed to correctly generate the devicetree headers
for use in other drivers (ie SSD1306).
Signed-off-by: Jeremy Herbert <jeremy.006@gmail.com>
Work around the fact that llvm objcopy does not support --gap-fill right
now. This should be done on the toolchain level at some point, it is
currently not possible however.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Don't allow user to choose CPU_ARCEM / CPU_ARCHS options
but select them when exact CPU type (i.e. EM4 / EM6 / HS3X/ etc)
is chosen.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add initial board support for the MPS3 AN547. The board support is
based on the MPS2+ AN521 board support.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since recent developments, CORTEX_M_SYSTICK should not be forced
on STM32L5 targets as this conflicts with optional LPTIM selection
as kernel tick source.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
