Enabling DAC support for STM32 nucleo_f767zi in device tree.
Documentation has been updated.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
This commit adds support for Silicon Labs BRD4255A (a.k.a. SLWRB4255A)
Flex Gecko Radio Board.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This is a follow-up to commit 763e73d7da.
Switch to the new properties for specifying SDA and SCL pins,
as the old ones (sda-pin and scl-pin) are now deprecated.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enable GPIO driver for Quick Feather board.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
Remove SPI_[0-8] and SPI_[0-8]_OP_MODES Kconfig symbols as no driver
uses them anymore. We also cleanup board and sample code to remove
use of these symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
MCUboot recently gives possibility to signal its state
using led.
For leverage this feature need to provide proper alias
for the led gpio pin.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Currently RAM region specified in the DT for board mps2-an512 to store
data (not to run code) is set to start at 0x3000_0000 and a 16M
contiguous space is assumed. However, at that address there is no such
contiguous space of 16M, rather only a 128K area is available. As a
consequence large applications linked with Zephyr might end up using
memory regions that are not valid, specially at runtime when the stack
grows, causing a BusFault.
Application Note 512 only specifies a 16M contiguous space available
starting at 0x8000_0000 (please see 'Table 3-4: SSRAM2 and SSRAM3
address mapping' and 'Table 3-6: External PSRAM mapping to Code Memory',
on pages 3-7 and 3-8, respectively), which resides in the PSRAM
(external RAM).
The AN521 also specifies a 4M contiguous space available starting at
0x3800_0000 which can be used as RAM for data storage and which is not
currently described in the DT.
The current DT also defines a 224M flash region (to run code) which
doesn't effectively exist, because most of it is reserved (~148M).
That commit fixes the incorrect definition of region 0x3000_0000 (16M)
and hence defines a new region called 'sram2_3' that maps to region
0x3800_0000 (4M) which is used as RAM to store data, and fixes the flash
region defining a new region 'sram1' (4M) from where code is executed
(starting at 0x1000_0000). The board has no real flash memory, rather an
auxilary HW populates the appropriate memory regions from images found
in a MicroSD card.
That commit also defines the missing PSRAM (16M) region ('psram') which
can be used by large programs as a general purpose RAM.
Finally, it also fixes the DT for the non-secure memory regions to
reflect the fixes described above for the secure memory regions.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
The mps2_an521_nonsecure exists for TFM and is also utilized as a config
for multicore samples. We can enable just the TFM tests with only_tags
and get a bit of additional coverage in QEMU for the TFM integration.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CORTEX_M_SYSTICK is enabled by default on all STM32 based targets,
in common soc Kconfig files.
Forcing its definition in board files is redundant and prevents
to disable it when activating LPTIM as ticker.
Remove these definitions
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This only fix several test cases failed while running code coverage
report inmps2_an385 platform. Enlarge the stack size for which failed
due to MPU fault of stack overflow.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
AArch64 has support for PSCI. This is especially useful for SMP because
PSCI is used to power on the secordary cores.
When the PSCI driver was introduced in Zephyr it was designed to rely on
a very PSCI-centric subsystem / interface.
There are two kinds of problems with this choice:
1. PSCI is only defined for the non-secure world and it is designed to
boot CPU cores into non-secure state (that means that PSCI is only
supposed to work if Zephyr is running in non-secure state)
2. There can be other ways or standards used to start / stop a core
different from PSCI
This patch is trying to fix the original wrong assumption by making the
interface / subsystem a generic one, called 'pm_cpu_ops', and using PSCI
only as an actual driver that is a user of this new interface /
subsystem.
For now the new subsystem is only exposing two methods: cpu_on and
cpu_off, others will probably follow according to the needs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
When instructed to flash the combined Secure and Non-Secure
binary, we need to modify the hex file used in west flash.
The combined binary is named tfm_merged.hex, regardless of
building with or without BL2.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In nRF5340, instruct the build to flash, by default, the
combined Secure (TF-M) and Non-Secure (Zephyr) binaries
as a merged binary, using west flash, if we are building
in-tree tests.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add devicetree node representing the PCAL6408A I2C-based I/O expander
that is available in nRF9160 DK v0.14.0 or later.
Provide also .dtsi files that can be used in applications to simplify
switching to interfacing onboard LEDs and buttons through this expander
instead of SoC pins.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the multiple board revisions feature to provide support for the new
hardware possibilities available in nRF9160 DK starting from v0.14.0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use devicetree instead of Kconfig to configure the board control
switches in nRF9160 DK:
- add binding for the switches that provide optional signal routings
on this board
- add binding for the GPIO interface that can be used for communication
(e.g. UART based) between the nRF9160 and the nRF52840 on the DK,
and add GPIO mapping for this interface so that its lines can be used
without caring about of actual pin numbers on both sides
- add binding for one GPIO line chosen from the above interface that is
to allow the nRF9160 to reset the nRF52840
- update accordingly dts files and board specific code for both board
definitions associated with the DK
- introduce .dtsi files that can be included from dts overlays in order
to facilitate the use of the above GPIO interface; modify the overlay
in the hci_uart sample to provide an example of use of those files
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Force the Arduino Due device to preform a reset after loading
the program using JLink, effectively allowing the program to
run after west flash.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Commit 821c03a14a ("i2c: nordic: switch
to phandle arrays for pinmux") deprecated some Nordic devicetree
properties.
When boards get merged with stale CI results (i.e. if CI results are
from a mainline commit earlier than 821c03a1), we will get deprecation
warnings, which twister treats as errors.
Play whack-a-mole with the ones that are in tree.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Enable the null-pointer dereferencing detection by default
throughout the test-suite. Explicitly disable this for the
gen_isr_table test which needs to perform vector table reads.
Disable null-pointer exception detection on qemu_cortex_m3
board, as DWT it is not emulated by QEMU on this platform.
Additionally, disable null-pointer exception detection on
mps2_an521 (QEMU target), as DWT is not present and the MPU
based solution won't work, since the target does not have
the area 0x0 - 0x400 mapped, but the QEMU still permits
read access.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Convert driver and users of pinmux on mcux lpc platforms to getting
basic port info from devicetree (register address, label)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the BOARD.dts files for Nordic-based boards to use the new I2C
devicetree properties for specifying the SDA and SCL pins.
This was done with a script.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add i2s as a supported feature on at least one board for each driver
that we have in tree to get CI coverage.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If CONFIG_I2C=n is set we get a build warning:
pinmux.c:35:13: error: 'i2c_pinmux' defined but not used
Fix this by adding ifdef protection around i2c_pinmux.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CONFIG_SPI_0 and CONFIG_SPI_0_OP_MODES aren't relevant for the
XEC QMSPI driver so remove setting them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add quadspi node in stm32f7.dtsi and quadspi support to boards
stm32f746g_disco and stm32f769i_disco.
Note! Does not support DMA.
Signed-off-by: Helge Juul <helge@fastmail.com>
Add pwm to board yaml as supported peripherals on the bbc_microbit.
This is needed as the servo_motor sample requires it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The board's main I2C bus controller doesn't have a compatible set, so
it's not detected as an I2C bus at all.
This breaks the build when trying to build the samples/sensor/lis2dh
application with the lis2dh sensor on that bus.
Fixes: #32420
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Place the new signing code in the TFM module CMakeLists.txt.
Make some small tweaks and add a sentence to the docs.
In the process, make a few changes to the signing code:
- Change some names of files created.
- Minimize the number of files created.
- Use hex files instead of bin files. This is so we don't need to know
the offset when creating hex files from bin files.
Also add signing for MCUBOOT_IMAGE_NUMBER=1 based on the code from the
v2m_musca_b1 board, though, this board does not build with =1 now
because of (I assume) some flash aliasing which places the S and NS
images 0x10000000 apart, where the manual algorithm places them next to
each other. It builds with =2, though.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
When proper target device is specified, instead of generic
Cortex-M33, JLinkGDBServer is able to flash the device on "load"
command.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Do not attempt to build/run all tests. Emulation platforms should
primarily build kernel and architecture related tests.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Quoting from the QEMU manual "MTTCG is not compatible with -icount and
enabling icount will force a single threaded run.". Given that for
Cortex-A53 we haven't seen any particular problem when disabling icount
try to disable it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
CLOCK_STM32_PLL_XTPRE Kconfig symbol default value is n.
Then there is no need to explicitly set it to 'n' in stm32f1 boards
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The choice allowed for using TFM's own default. We now need full
knowledge over whether BL2 is enabled or not (e.g. to do signing),
so remove this option and simplify to a bool.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Add the missing pieces to enable XIP for AArch64. Try to simulate the
XIP using QEMU using the '-bios' parameter.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Provide the arduino_i2c node name from i2c_0.
Provide pinmux for frdm_stbc_agm01.
The frdm_stbc_agm01 supplies access to an FXOS8700 and FXAS21002.
when using frdm_stbc_agm01 with frdm_k22f, the FXAS21002 sample
sensor project can be utilized and the FXOS8700 sample sensor
project utilizes the shield's FXOS8700.
Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
Even though possible to use external pull-up and open drain buffer,
prefer internal pull-up to reduce power consumption.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
This commit moves TFM CMakeLists.txt into Zephyr and relocates the
Kconfig.tfm file under the modules/tfm folder.
Updates the manifest to point to related TFM changes.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Remove support for the Musca-A board. This board is rarely used, few
are available and superceded by Musca-B and Musca-S.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This CL moves def_lvol_io_list device-tree node from npcx7m6fb_evb.dts
to npcx7m6fb.dtsi. The benefit of it is that we needn't add
def_lvol_io_list node for each board dts file if there are no 1.8V
io-pads on the platform. If so, add them in the specific board dts file
directly.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
- Updated arduino dtsi to map spi1 as arduino spi
- Made board's zephyr peripheral mapping more compact and added arduino
and st-link labels.
Signed-off-by: Nikos Oikonomou <nikoikonomou92@gmail.com>
Set the Zephyr Vendor Specific HCI extensions as default y on nRF boards
that only support host only builds.
Correct this for nrf5340dk which had set the Kconfig for the feature
support instead of the feature itself.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
nRF5340 PDK board was deprecated in v2.5.0 release
and is removed now from the tree.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Stm32f7 disco boards benefit from dedicated openocd board target.
Use these target as the generic stm32f7discovery one will be
eventually removed.
Additionally, replace now deprecated 'adapter_khz' by 'adapter speed'.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
All of these boards can be debugged with west debug via settings in
board.cmake, but the docs say they can't be. This is being copy/pasted
around; fix it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Increase the size of ram/flash given in nrf5340dk_nrf5340_cpuapp.yaml
so they match the actual numbers which are available for default
tests and samples.
Signed-off-by: Maciej Perkowski <Maciej.Perkowski@nordicsemi.no>
A number of SoCs have overlapping devices at the same unit address.
Surpress the warning for those cases:
* NRF - kmu@39000 & flash-controller@39000
* NRF - clock@5000 & power@5000
* NRF - image@20000000 & image_s@20000000
* NRF - i2c@40003000 & spi@40003000
* STM - i2s@40003800 & spi@40003800
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
A number of SoCs have overlapping devices at the same unit address.
Surpress the warning for those cases:
* Atmel - pinmux@41004400 & gpio@41004400
* Atmel - pinmux@41004480 & gpio@41004480
* Atmel - pinmux@41008000 & gpio@41008000
* NXP - flash@0 & gpio@0
* NXP - syscon@0 & gpio@0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On Atmel & Silabs SoCs the SPI controller is implemented on a shared
peripheral block (sercom for atmel, usart on silabs) so we can't have
the node name be "spi@...". In these cases we disable the warning
via passing '-Wno-spi_bus_bridge' to dtc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
