Properly dereference the value pointer in assignment.
```
In function 'gpio_pca_series_port_read_standard':
warning: assignment to 'gpio_port_value_t *' {aka 'unsigned int *'} \
from 'uint32_t' {aka 'unsigned int'} makes pointer from integer \
without a cast [-Wint-conversion]
1071 | value = sys_le32_to_cpu(input_data);
| ^
```
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Move the direction reset to config init function. This ensures that regs
is read after the DEVICE_MMIO_NAMED_MAP is called, which is where the
init for RAM MMIO takes place
Tested on PocketBeagle 2 A53s.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
The nRF GPIO hardware does not store the initial output value
set resulting from gpio_pin_configure() and thus, when
gpio_get_config() is used, the initial value is not returned.
This commit just reads the output value and sets the INIT
value to match in gpio_get_config().
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Mass renaming is carried out to unify some prefixes and shorten some
macros, making the code easier to maintain and support new devices.
- Rename `int_dev` to `gpio_int_dev` for gpio interrupt
- Rename `eirq` to `ext_irq` for external interrupt
- Rename `gpio_rz_hw_config` to `gpio_rz_flags`
- Rename `p_pm` to `gpio_flags`
- Rename `pre_flags` to `rz_flags`
- Remove `_IOPORT` and `_PIN_CONFIGURE` in some macros
- Rename `GPIO_RZ_PIN_CONFIGURE_GET_FILTER`,
`GPIO_RZ_PIN_CONFIGURE_GET`, `GPIO_RZ_PIN_SPECIAL_FLAG_GET` to
`GPIO_RZ_FLAG_GET_FILTER`, `GPIO_RZ_FLAG_GET_CONFIG`,
`GPIO_RZ_FLAG_GET_SPECIFIC` respectively
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit adds a padding of 0x10 bytes at the beginning of the
`gpio_davinci_regs` structure to correctly align the register
definitions with the actual register layout.
Previously, the DTS had to manually offset the base address by
0x10, introducing a special case in Zephyr's Davinci GPIO driver.
This change eliminates the need for that workaround
Adding the paddingi also help to maintain a similarly with also
to the linux counterpart.
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
Change the base address of GPIO and pinctrl voltage selection
The new base address enables more pins to support voltage selection.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This driver was setting all GPIO lines to input and the data register to
zero on initialization. This does not appear to be common practice among
other GPIO drivers, and in fact caused a serious problem on the ZynqMP
platform, where between 1 and 4 of the top-most GPIO lines are
frequently used by platform firmware and Vivado as reset lines for the
programmable logic. Since these resets are active low, and their
input/output state is ignored due to how they are connected to the EMIO
GPIO outputs from the PS, this caused the PL reset to be asserted when
the GPIO driver initialized, preventing any logic using that reset from
functioning properly.
There may also be other cases where GPIO line states have already been
set by the boot loader or firmware and clearing them may result in
improper behavior or glitches on the lines during initialization.
Update the driver to disable GPIO interrupts but leave the pin
modes/states unchanged until/unless they are explicitly reconfigured.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The Kconfig help text for the SN74HC595 driver refers to the device
as a "GPIO extender", which is inconsistent with the devicetree
binding file (ti,sn74hc595.yaml) that describes it as a "GPIO expander".
Signed-off-by: Hank Wang <wanghanchi2000@gmail.com>
Initial commit for GPIO driver support on board using RX130 MCUs
* drivers: GPIO: implementation for GPIO driver on RSK_RX130_512KB
* dts: rx: add device node for GPIO of RSK_RX130_512KB
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Don't automatically disable all GPIO ports just because
`PM_DEVICE_RUNTIME` is enabled. Require the user to explicitly call
`pm_device_runtime_enable` on the port, or add
`zephyr,pm-device-runtime-auto` to the devicetree node.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The i.MXRT10xx series have configurable GPIO pull strengths.
These are available for configuration in the pinctrl system, but not for
regular GPIO use.
This commit adds SOC-series specific GPIO configuration bits for selecting
weak or strong GPIO pulls, similar to drive strengths available from other
GPIO pin configuration examples.
This has been tested on a custom i.MXRT1062 product.
Signed-off-by: Stefan Giroux <stefan.g@feniex.com>
Driver is using local macro to get current CPU ID and it is now
in conflict with generic CPU_ID. Added prefix to avoid conflict.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The PCAL6534 driver simply doesn't work. This is
due to an incorrect mapping of commands to pcal6534
registers.
Signed-off-by: Victor Brzeski <vbrzeski@meta.com>
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fix two instances where switch-case labels were followed immediately by
a declaration, which is generally invalid and can cause compilation
failure.
Signed-off-by: Kesavan Yogeswaran <hikes@google.com>
- Add spaces around /* ... */
- Fix a typo and remove a stray space in the description of
renesas,rz-gpio.yaml to make it visible in doc html
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
The MAX22199 is an IEC 61131-2 compliant industrial digital input device.
The MAX22199 translates eight 24V current-sinking industrial inputs to a
serialized SPI-compatible output that interfaces with 3V to 5.5V logic. It
can operate as eight Type 1/Type 3 digital inputs or four Type 2 digital
inputs. The device provides diagnostic functions, including thermal
shutdown, 24V under voltage alarm, 24V missing voltage alarm, and SPI and
CRC communication error detection.
Signed-off-by: Robert Budai <robert.budai@analog.com>
MAX14917 is an eight high-side switch, specified to deliver up to 700mA
(min) continuous current per channel. The high-side switches have
on-resistance of 120mΩ (typ) at 25°C ambient temperature
Signed-off-by: Robert Budai <robert.budai@analog.com>
Before that fix we read the inpupt register when toggling
gpios. With this fix, we now read the output register for
toggling a pin.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Add GPIO driver support for RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Due to historical reasons, there were two implementations of
R7FA4M1AB3CFM. However, the migration has been completed,
so the old one is now being removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This reverts commit 99e7223a1c.
Breaks CI with the following compilation error in SPI.c:52:
error: 'SPI_MASTER' undeclared here (not in a function)
Failing tests (cc3220sf_launchxl/cc3220sf)
- sample.net.sockets.echo.offload.simplelink
- sample.net.sockets.http_get.offload.simplelink
- sample.net.wifi
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Zephyr GPIO drivers require the pin mask `struct gpio_driver_data` to be
the first element of the driver config. Reordering fixes failures in ASSERT
statements of the GPIO driver due to the base address being interpreted as
supported pin mask.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
- It seems that the mask variants of GPIO functions are not present in
the latest sdk, so replace those with direct register access.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
As the RP2350B has more than 32 GPIO pins,
we changed the configuration so that it is split into two ports.
To do this, we created a `raspberrypi,pico-gpio-port` node and
moved the previous `raspberrypi,pico-gpio-port` functions to it.
This became a child node of `raspberrypi,pico-gpio-port`, and
`raspberrypi,pico-gpio-port` will remain a gpio mapper.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32
v1.11.1. Notable changes include:
- Optional RISC-V ISA Kconfigs are now selected on the board level.
- Peripheral registers are now automatically reset in hardware, no need for
software initialization code.
- The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt
support will be submitted in a separate PR.
- Default board configuration has 64k RAM and is clocked at 18 MHz.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
