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drivers/pinmux: stm32: Control GPIO clock with central function

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Use new gpio_stm32_clock_request function for GPIO clocks control.
To do this a new table of GPIO devices is set up at build time.
It is then used to populate targeted device when calling
gpio_stm32_clock_request.

Clean up remaining clock handling related code in the file.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-02-17 11:13:09 +01:00 committed by Kumar Gala
parent 6b2ccbb721
commit 8d97f67159
2 changed files with 29 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

112
drivers/pinmux/stm32/pinmux_stm32.c
View File

@ -31,80 +31,25 @@
#endif /* CONFIG_SOC_SERIES_STM32MP1X */
/* base address for where GPIO registers start */
#define GPIO_PORTS_BASE (GPIOA_BASE)
#define GPIO_DEVICE(gpio_port) \
COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_port), okay), \
(DEVICE_DT_GET(DT_NODELABEL(gpio_port))), \
((const struct device *)NULL))
static const uint32_t ports_enable[STM32_PORTS_MAX] = {
STM32_PERIPH_GPIOA,
STM32_PERIPH_GPIOB,
STM32_PERIPH_GPIOC,
#ifdef GPIOD_BASE
STM32_PERIPH_GPIOD,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOE_BASE
STM32_PERIPH_GPIOE,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOF_BASE
STM32_PERIPH_GPIOF,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOG_BASE
STM32_PERIPH_GPIOG,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOH_BASE
STM32_PERIPH_GPIOH,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOI_BASE
STM32_PERIPH_GPIOI,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOJ_BASE
STM32_PERIPH_GPIOJ,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
#ifdef GPIOK_BASE
STM32_PERIPH_GPIOK,
#else
STM32_PORT_NOT_AVAILABLE,
#endif
const struct device * const gpio_ports[STM32_PORTS_MAX] = {
GPIO_DEVICE(gpioa),
GPIO_DEVICE(gpiob),
GPIO_DEVICE(gpioc),
GPIO_DEVICE(gpiod),
GPIO_DEVICE(gpioe),
GPIO_DEVICE(gpiof),
GPIO_DEVICE(gpiog),
GPIO_DEVICE(gpioh),
GPIO_DEVICE(gpioi),
GPIO_DEVICE(gpioj),
GPIO_DEVICE(gpiok),
};
/**
* @brief enable IO port clock
*
* @param port I/O port ID
* @param clk optional clock device
*
* @return 0 on success, error otherwise
*/
static int enable_port(uint32_t port, const struct device *clk)
{
/* enable port clock */
if (!clk) {
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
}
struct stm32_pclken pclken;
pclken.bus = STM32_CLOCK_BUS_GPIO;
pclken.enr = ports_enable[port];
if (pclken.enr == STM32_PORT_NOT_AVAILABLE) {
return -EIO;
}
return clock_control_on(clk, (clock_control_subsys_t *) &pclken);
}
static int stm32_pin_configure(uint32_t pin, uint32_t func, uint32_t altf)
{
/* determine IO port registers location */
@ -131,9 +76,10 @@ static int stm32_pin_configure(uint32_t pin, uint32_t func, uint32_t altf)
int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
size_t list_size, uint32_t base)
{
const struct device *clk;
const struct device *port_device;
uint32_t pin, mux;
uint32_t func = 0;
int ret = 0;
if (!list_size) {
/* Empty pinctrl. Exit */
@ -149,9 +95,6 @@ int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
ARG_UNUSED(base);
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
/* make sure to enable port clock first */
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
for (int i = 0; i < list_size; i++) {
mux = pinctrl[i].pinmux;
@ -189,8 +132,12 @@ int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
pin = STM32PIN(STM32_DT_PINMUX_PORT(mux),
STM32_DT_PINMUX_LINE(mux));
port_device = gpio_ports[STM32_PORT(pin)];
enable_port(STM32_PORT(pin), clk);
ret = gpio_stm32_clock_request(port_device, true);
if (ret != 0) {
return ret;
}
stm32_pin_configure(pin, func, STM32_DT_PINMUX_FUNC(mux));
}
@ -447,11 +394,12 @@ int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
*
* @return 0 on success, error otherwise
*/
int z_pinmux_stm32_set(uint32_t pin, uint32_t func,
const struct device *clk)
int z_pinmux_stm32_set(uint32_t pin, uint32_t func)
{
const struct device *port_device = gpio_ports[STM32_PORT(pin)];
/* make sure to enable port clock first */
if (enable_port(STM32_PORT(pin), clk)) {
if (gpio_stm32_clock_request(port_device, true)) {
return -EIO;
}
@ -467,14 +415,10 @@ int z_pinmux_stm32_set(uint32_t pin, uint32_t func,
void stm32_setup_pins(const struct pin_config *pinconf,
size_t pins)
{
const struct device *clk;
int i;
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
for (i = 0; i < pins; i++) {
z_pinmux_stm32_set(pinconf[i].pin_num,
pinconf[i].mode,
clk);
pinconf[i].mode);
}
}

3
drivers/pinmux/stm32/pinmux_stm32.h
View File

@ -125,8 +125,7 @@ clock_control_subsys_t stm32_get_port_clock(int port);
* @param clk clock control device, for enabling/disabling clock gate
* for the port
*/
int z_pinmux_stm32_set(uint32_t pin, uint32_t func,
const struct device *clk);
int z_pinmux_stm32_set(uint32_t pin, uint32_t func);
/**
* @brief helper for obtaining pin configuration for the board