This commit adds ambiq iom binding file to consolidate
spi and i2c that share the same IO Master module on
Apollo MCUs
Signed-off-by: Hao Luo <hluo@ambiq.com>
This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Renesas takes over the maintainer of SoC Renesas RZ/T2M to unify with
other RZ devices
- Move soc/renesas/rzt2m to soc/renesas/rz
- Support xSPI boot mode to boot code from flash
- Change to use HAL Renesas
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
add mdio and phy node to every stm32board that
supports ethernet.
Also set the phy-handle for every ethernet mac.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Fix USB controller base address.
rp2040 was fixed in a10f2e8 and the rp2350 uses the same base address.
Signed-off-by: James Turton <james.turton@gmx.com>
- Fixes declared memory region sizes in .yaml and .rst.
- Adds SRAMX linker region.
- The lpcxpresso55s36 linker memory regions are:
FLASH =246KB, RAM=112KB, SRAMX=16KB.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Since this SoC is equivalent to the STM32F429 SoC, simply include its
device tree and add the 'cryp' node for the hardware cryptographic
accelerator.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add support for the RPU, real-time processing unit on Versal NET SoC.
It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board
with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global
timer and UART.
versalnet.dtsi contains common peripherals integrated into Versal NET
SoC, and versalnet_r52.dtsi has peripherals which are private to
Cortex-R52 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Define Ethernet and MDIO nodes in the RA6 Cortex-M33 SoC device tree
files in a similar manner to the RA8 SoC device tree files.
Removed those nodes from R6E2 SoC as it does not have Ethernet support.
Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
- Add new device tree source include file for DA14697 SoC
- Update Kconfig and soc.yml to support the new device
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
This commit to add i2c device node to support i2c sci-b driver
on Renesas RA SoCs
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
The Messaging Unit 7 peripheral is made available for
use with IPC such as OpenAMP/RpMsg. MU7 connects
to the A55 core
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
This commit changes to use ambiq hal power control APIs
to replace the previous register settings to power on
ambiq drivers.
Signed-off-by: Hao Luo <hluo@ambiq.com>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Currently, siwx917 have three instances of uart: ulpuart, uart1 and
uart2. However:
- The other drivers on siwx91x (i2c, dma, i2s, etc...) rather use
'ulp', '0' and '1'.
- The reference manual also uses 'ulp', '0' and '1'.
The source of the confusion probably come from the clock driver in
WiseConnect which use clocks USART1 and USART2. However, this probably
not expected.
So, this patch renames uart1 and uart2 in uart0 and uart1. This change
also impacts the names of pins and the names of the clocks.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
