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soc: silabs: siwx91x: Rename UART instances

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Currently, siwx917 have three instances of uart: ulpuart, uart1 and
uart2. However:

  - The other drivers on siwx91x (i2c, dma, i2s, etc...) rather use
    'ulp', '0' and '1'.

  - The reference manual also uses 'ulp', '0' and '1'.

The source of the confusion probably come from the clock driver in
WiseConnect which use clocks USART1 and USART2. However, this probably
not expected.

So, this patch renames uart1 and uart2 in uart0 and uart1. This change
also impacts the names of pins and the names of the clocks.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This commit is contained in:
Jérôme Pouiller 2025-03-14 12:06:00 +01:00 committed by Benjamin Cabé
parent 1f73ca3919
commit 8894fa42c0
4 changed files with 99 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/clock_control/clock_control_silabs_siwx91x.c
View File

@ -45,12 +45,12 @@ static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys
RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA);
RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK);
break;
case SIWX91X_CLK_UART1:
case SIWX91X_CLK_UART0:
RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */
RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART1, 0, 1);
break;
case SIWX91X_CLK_UART2:
case SIWX91X_CLK_UART1:
RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */
RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART2, 0, 1);
@ -97,10 +97,10 @@ static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sy
case SIWX91X_CLK_ULP_DMA:
RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_UDMA_CLK);
break;
case SIWX91X_CLK_UART1:
case SIWX91X_CLK_UART0:
RSI_CLK_PeripheralClkDisable(M4CLK, USART1_CLK);
break;
case SIWX91X_CLK_UART2:
case SIWX91X_CLK_UART1:
RSI_CLK_PeripheralClkDisable(M4CLK, USART2_CLK);
break;
case SIWX91X_CLK_DMA0:
@ -128,10 +128,10 @@ static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys
case SIWX91X_CLK_ULP_UART:
*rate = RSI_CLK_GetBaseClock(ULPSS_UART);
return 0;
case SIWX91X_CLK_UART1:
case SIWX91X_CLK_UART0:
*rate = RSI_CLK_GetBaseClock(M4_USART0);
return 0;
case SIWX91X_CLK_UART2:
case SIWX91X_CLK_UART1:
*rate = RSI_CLK_GetBaseClock(M4_UART1);
return 0;
case SIWX91X_CLK_PWM:

8
dts/arm/silabs/siwg917.dtsi
View File

@ -78,22 +78,22 @@
status = "disabled";
};
uart1: uart@44000000 {
uart0: uart@44000000 {
compatible = "ns16550";
reg = <0x44000000 0x1000>;
interrupts = <38 0>;
reg-shift = <2>;
clocks = <&clock0 SIWX91X_CLK_UART1>;
clocks = <&clock0 SIWX91X_CLK_UART0>;
current-speed = <115200>;
status = "disabled";
};
uart2: uart@45020000 {
uart1: uart@45020000 {
compatible = "ns16550";
reg = <0x45020000 0x1000>;
interrupts = <39 0>;
reg-shift = <2>;
clocks = <&clock0 SIWX91X_CLK_UART2>;
clocks = <&clock0 SIWX91X_CLK_UART1>;
current-speed = <115200>;
status = "disabled";
};

4
include/zephyr/dt-bindings/clock/silabs/siwx91x-clock.h
View File

@ -7,8 +7,8 @@
#define SIWX91X_CLK_ULP_UART 0
#define SIWX91X_CLK_ULP_I2C 1
#define SIWX91X_CLK_ULP_DMA 2
#define SIWX91X_CLK_UART1 3
#define SIWX91X_CLK_UART2 4
#define SIWX91X_CLK_UART0 3
#define SIWX91X_CLK_UART1 4
#define SIWX91X_CLK_I2C0 5
#define SIWX91X_CLK_I2C1 6
#define SIWX91X_CLK_DMA0 7

174
include/zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h
View File

@ -404,94 +404,94 @@
#define TRACE_D3_PD3 SIWX91X_GPIO(6, 0xFF, 15, 3, 3, 0)
#define TRACE_D3_PD9 SIWX91X_GPIO(6, 0xFF, 21, 3, 9, 0)
#define UART1_CLK_PA8 SIWX91X_GPIO(2, 0xFF, 3, 0, 8, 0)
#define UART1_CLK_PB9 SIWX91X_GPIO(2, 0xFF, 0, 1, 9, 0)
#define UART1_CLK_PD4 SIWX91X_GPIO(2, 0xFF, 16, 3, 4, 0)
#define UART1_CLK_ULP0 SIWX91X_GPIO(2, 6, 22, 4, 0, 0)
#define UART1_CTS_PA6 SIWX91X_GPIO(2, 0xFF, 1, 0, 6, 0)
#define UART1_CTS_PB10 SIWX91X_GPIO(2, 0xFF, 0, 1, 10, 0)
#define UART1_CTS_PD8 SIWX91X_GPIO(2, 0xFF, 20, 3, 8, 0)
#define UART1_CTS_ULP6 SIWX91X_GPIO(2, 6, 28, 4, 6, 6)
#define UART1_DCD_PA12 SIWX91X_GPIO(2, 0xFF, 7, 0, 12, 0)
#define UART1_DCD_PB13 SIWX91X_GPIO(12, 0xFF, 0, 1, 13, 0)
#define UART1_DSR_PA11 SIWX91X_GPIO(2, 0xFF, 6, 0, 11, 0)
#define UART1_DSR_PD9 SIWX91X_GPIO(2, 0xFF, 21, 3, 9, 0)
#define UART1_DTR_PA7 SIWX91X_GPIO(2, 0xFF, 2, 0, 7, 0)
#define UART1_IRRX_PB9 SIWX91X_GPIO(13, 0xFF, 0, 1, 9, 0)
#define UART1_IRRX_PC15 SIWX91X_GPIO(2, 0xFF, 11, 2, 15, 0)
#define UART1_IRRX_ULP0 SIWX91X_GPIO(11, 6, 22, 4, 0, 0)
#define UART1_IRRX_ULP7 SIWX91X_GPIO(2, 6, 29, 4, 7, 7)
#define UART1_IRTX_PB10 SIWX91X_GPIO(13, 0xFF, 0, 1, 10, 0)
#define UART1_IRTX_PD0 SIWX91X_GPIO(2, 0xFF, 12, 3, 0, 0)
#define UART1_IRTX_ULP1 SIWX91X_GPIO(11, 6, 23, 4, 1, 1)
#define UART1_IRTX_ULP8 SIWX91X_GPIO(2, 6, 30, 4, 8, 8)
#define UART1_RI_PB11 SIWX91X_GPIO(2, 0xFF, 0, 1, 11, 0)
#define UART1_RI_PC14 SIWX91X_GPIO(2, 0xFF, 10, 2, 14, 0)
#define UART1_RI_ULP4 SIWX91X_GPIO(11, 6, 26, 4, 4, 4)
#define UART1_RS485DE_PB13 SIWX91X_GPIO(13, 0xFF, 0, 1, 13, 0)
#define UART1_RS485DE_PD3 SIWX91X_GPIO(2, 0xFF, 15, 3, 3, 0)
#define UART1_RS485DE_ULP7 SIWX91X_GPIO(11, 6, 29, 4, 7, 7)
#define UART1_RS485DE_ULP11 SIWX91X_GPIO(2, 6, 33, 4, 11, 11)
#define UART1_RS485EN_PB11 SIWX91X_GPIO(13, 0xFF, 0, 1, 11, 0)
#define UART1_RS485EN_PD1 SIWX91X_GPIO(2, 0xFF, 13, 3, 1, 0)
#define UART1_RS485EN_ULP5 SIWX91X_GPIO(11, 6, 27, 4, 5, 5)
#define UART1_RS485EN_ULP9 SIWX91X_GPIO(2, 6, 31, 4, 9, 9)
#define UART1_RS485RE_PB12 SIWX91X_GPIO(13, 0xFF, 0, 1, 12, 0)
#define UART1_RS485RE_PD2 SIWX91X_GPIO(2, 0xFF, 14, 3, 2, 0)
#define UART1_RS485RE_ULP6 SIWX91X_GPIO(11, 6, 28, 4, 6, 6)
#define UART1_RS485RE_ULP10 SIWX91X_GPIO(2, 6, 32, 4, 10, 10)
#define UART1_RTS_PA9 SIWX91X_GPIO(2, 0xFF, 4, 0, 9, 0)
#define UART1_RTS_PB12 SIWX91X_GPIO(2, 0xFF, 0, 1, 12, 0)
#define UART1_RTS_PD5 SIWX91X_GPIO(2, 0xFF, 17, 3, 5, 0)
#define UART1_RTS_ULP5 SIWX91X_GPIO(2, 6, 27, 4, 5, 5)
#define UART1_RX_PA10 SIWX91X_GPIO(2, 0xFF, 5, 0, 10, 0)
#define UART1_RX_PB13 SIWX91X_GPIO(2, 0xFF, 0, 1, 13, 0)
#define UART1_RX_PD7 SIWX91X_GPIO(2, 0xFF, 19, 3, 7, 0)
#define UART1_RX_ULP1 SIWX91X_GPIO(2, 6, 23, 4, 1, 1)
#define UART1_RX_ULP6 SIWX91X_GPIO(4, 6, 28, 4, 6, 6)
#define UART1_TX_PB14 SIWX91X_GPIO(2, 0xFF, 0, 1, 14, 0)
#define UART1_TX_PD6 SIWX91X_GPIO(2, 0xFF, 18, 3, 6, 0)
#define UART1_TX_ULP4 SIWX91X_GPIO(2, 6, 26, 4, 4, 4)
#define UART1_TX_ULP7 SIWX91X_GPIO(4, 6, 29, 4, 7, 7)
#define UART0_CLK_PA8 SIWX91X_GPIO(2, 0xFF, 3, 0, 8, 0)
#define UART0_CLK_PB9 SIWX91X_GPIO(2, 0xFF, 0, 1, 9, 0)
#define UART0_CLK_PD4 SIWX91X_GPIO(2, 0xFF, 16, 3, 4, 0)
#define UART0_CLK_ULP0 SIWX91X_GPIO(2, 6, 22, 4, 0, 0)
#define UART0_CTS_PA6 SIWX91X_GPIO(2, 0xFF, 1, 0, 6, 0)
#define UART0_CTS_PB10 SIWX91X_GPIO(2, 0xFF, 0, 1, 10, 0)
#define UART0_CTS_PD8 SIWX91X_GPIO(2, 0xFF, 20, 3, 8, 0)
#define UART0_CTS_ULP6 SIWX91X_GPIO(2, 6, 28, 4, 6, 6)
#define UART0_DCD_PA12 SIWX91X_GPIO(2, 0xFF, 7, 0, 12, 0)
#define UART0_DCD_PB13 SIWX91X_GPIO(12, 0xFF, 0, 1, 13, 0)
#define UART0_DSR_PA11 SIWX91X_GPIO(2, 0xFF, 6, 0, 11, 0)
#define UART0_DSR_PD9 SIWX91X_GPIO(2, 0xFF, 21, 3, 9, 0)
#define UART0_DTR_PA7 SIWX91X_GPIO(2, 0xFF, 2, 0, 7, 0)
#define UART0_IRRX_PB9 SIWX91X_GPIO(13, 0xFF, 0, 1, 9, 0)
#define UART0_IRRX_PC15 SIWX91X_GPIO(2, 0xFF, 11, 2, 15, 0)
#define UART0_IRRX_ULP0 SIWX91X_GPIO(11, 6, 22, 4, 0, 0)
#define UART0_IRRX_ULP7 SIWX91X_GPIO(2, 6, 29, 4, 7, 7)
#define UART0_IRTX_PB10 SIWX91X_GPIO(13, 0xFF, 0, 1, 10, 0)
#define UART0_IRTX_PD0 SIWX91X_GPIO(2, 0xFF, 12, 3, 0, 0)
#define UART0_IRTX_ULP1 SIWX91X_GPIO(11, 6, 23, 4, 1, 1)
#define UART0_IRTX_ULP8 SIWX91X_GPIO(2, 6, 30, 4, 8, 8)
#define UART0_RI_PB11 SIWX91X_GPIO(2, 0xFF, 0, 1, 11, 0)
#define UART0_RI_PC14 SIWX91X_GPIO(2, 0xFF, 10, 2, 14, 0)
#define UART0_RI_ULP4 SIWX91X_GPIO(11, 6, 26, 4, 4, 4)
#define UART0_RS485DE_PB13 SIWX91X_GPIO(13, 0xFF, 0, 1, 13, 0)
#define UART0_RS485DE_PD3 SIWX91X_GPIO(2, 0xFF, 15, 3, 3, 0)
#define UART0_RS485DE_ULP7 SIWX91X_GPIO(11, 6, 29, 4, 7, 7)
#define UART0_RS485DE_ULP11 SIWX91X_GPIO(2, 6, 33, 4, 11, 11)
#define UART0_RS485EN_PB11 SIWX91X_GPIO(13, 0xFF, 0, 1, 11, 0)
#define UART0_RS485EN_PD1 SIWX91X_GPIO(2, 0xFF, 13, 3, 1, 0)
#define UART0_RS485EN_ULP5 SIWX91X_GPIO(11, 6, 27, 4, 5, 5)
#define UART0_RS485EN_ULP9 SIWX91X_GPIO(2, 6, 31, 4, 9, 9)
#define UART0_RS485RE_PB12 SIWX91X_GPIO(13, 0xFF, 0, 1, 12, 0)
#define UART0_RS485RE_PD2 SIWX91X_GPIO(2, 0xFF, 14, 3, 2, 0)
#define UART0_RS485RE_ULP6 SIWX91X_GPIO(11, 6, 28, 4, 6, 6)
#define UART0_RS485RE_ULP10 SIWX91X_GPIO(2, 6, 32, 4, 10, 10)
#define UART0_RTS_PA9 SIWX91X_GPIO(2, 0xFF, 4, 0, 9, 0)
#define UART0_RTS_PB12 SIWX91X_GPIO(2, 0xFF, 0, 1, 12, 0)
#define UART0_RTS_PD5 SIWX91X_GPIO(2, 0xFF, 17, 3, 5, 0)
#define UART0_RTS_ULP5 SIWX91X_GPIO(2, 6, 27, 4, 5, 5)
#define UART0_RX_PA10 SIWX91X_GPIO(2, 0xFF, 5, 0, 10, 0)
#define UART0_RX_PB13 SIWX91X_GPIO(2, 0xFF, 0, 1, 13, 0)
#define UART0_RX_PD7 SIWX91X_GPIO(2, 0xFF, 19, 3, 7, 0)
#define UART0_RX_ULP1 SIWX91X_GPIO(2, 6, 23, 4, 1, 1)
#define UART0_RX_ULP6 SIWX91X_GPIO(4, 6, 28, 4, 6, 6)
#define UART0_TX_PB14 SIWX91X_GPIO(2, 0xFF, 0, 1, 14, 0)
#define UART0_TX_PD6 SIWX91X_GPIO(2, 0xFF, 18, 3, 6, 0)
#define UART0_TX_ULP4 SIWX91X_GPIO(2, 6, 26, 4, 4, 4)
#define UART0_TX_ULP7 SIWX91X_GPIO(4, 6, 29, 4, 7, 7)
#define UART2_CTS_PA11 SIWX91X_GPIO(6, 0xFF, 6, 0, 11, 0)
#define UART2_CTS_PC0 SIWX91X_GPIO(12, 0xFF, 9, 2, 0, 0)
#define UART2_CTS_PD3 SIWX91X_GPIO(9, 0xFF, 15, 3, 3, 0)
#define UART2_CTS_ULP1 SIWX91X_GPIO(9, 6, 23, 4, 1, 1)
#define UART2_CTS_ULP7 SIWX91X_GPIO(6, 6, 29, 4, 7, 7)
#define UART2_CTS_ULP9 SIWX91X_GPIO(9, 6, 31, 4, 9, 9)
#define UART2_RS485DE_PA9 SIWX91X_GPIO(6, 0xFF, 4, 0, 9, 0)
#define UART2_RS485DE_ULP2 SIWX91X_GPIO(6, 6, 24, 4, 2, 2)
#define UART2_RS485DE_ULP11 SIWX91X_GPIO(6, 6, 33, 4, 11, 11)
#define UART2_RS485EN_PA12 SIWX91X_GPIO(6, 0xFF, 7, 0, 12, 0)
#define UART2_RS485EN_PB10 SIWX91X_GPIO(6, 0xFF, 0, 1, 10, 0)
#define UART2_RS485EN_ULP0 SIWX91X_GPIO(6, 6, 22, 4, 0, 0)
#define UART2_RS485RE_PA8 SIWX91X_GPIO(6, 0xFF, 3, 0, 8, 0)
#define UART2_RS485RE_ULP1 SIWX91X_GPIO(6, 6, 23, 4, 1, 1)
#define UART2_RS485RE_ULP10 SIWX91X_GPIO(6, 6, 32, 4, 10, 10)
#define UART2_RTS_PA10 SIWX91X_GPIO(6, 0xFF, 5, 0, 10, 0)
#define UART2_RTS_PB11 SIWX91X_GPIO(6, 0xFF, 0, 1, 11, 0)
#define UART2_RTS_PB12 SIWX91X_GPIO(6, 0xFF, 0, 1, 12, 0)
#define UART2_RTS_PB15 SIWX91X_GPIO(12, 0xFF, 9, 1, 15, 0)
#define UART2_RTS_PD2 SIWX91X_GPIO(9, 0xFF, 14, 3, 2, 0)
#define UART2_RTS_ULP0 SIWX91X_GPIO(9, 6, 22, 4, 0, 0)
#define UART2_RTS_ULP6 SIWX91X_GPIO(6, 6, 28, 4, 6, 6)
#define UART2_RTS_ULP8 SIWX91X_GPIO(9, 6, 30, 4, 8, 8)
#define UART2_RX_PA6 SIWX91X_GPIO(6, 0xFF, 1, 0, 6, 0)
#define UART2_RX_PB13 SIWX91X_GPIO(6, 0xFF, 0, 1, 13, 0)
#define UART2_RX_PC1 SIWX91X_GPIO(12, 0xFF, 9, 2, 1, 0)
#define UART2_RX_ULP2 SIWX91X_GPIO(9, 6, 24, 4, 1, 1)
#define UART2_RX_ULP4 SIWX91X_GPIO(6, 6, 26, 4, 4, 4)
#define UART2_RX_ULP8 SIWX91X_GPIO(6, 6, 30, 4, 8, 8)
#define UART2_RX_ULP10 SIWX91X_GPIO(9, 6, 32, 4, 10, 10)
#define UART2_TX_PA15 SIWX91X_GPIO(2, 0xFF, 8, 0, 15, 0)
#define UART2_TX_PA7 SIWX91X_GPIO(6, 0xFF, 2, 0, 7, 0)
#define UART2_TX_PB14 SIWX91X_GPIO(6, 0xFF, 0, 1, 14, 0)
#define UART2_TX_PC2 SIWX91X_GPIO(12, 0xFF, 9, 2, 2, 0)
#define UART2_TX_ULP3 SIWX91X_GPIO(9, 6, 25, 4, 1, 1)
#define UART2_TX_ULP5 SIWX91X_GPIO(6, 6, 27, 4, 5, 5)
#define UART2_TX_ULP9 SIWX91X_GPIO(6, 6, 31, 4, 9, 9)
#define UART2_TX_ULP11 SIWX91X_GPIO(9, 6, 33, 4, 11, 11)
#define UART1_CTS_PA11 SIWX91X_GPIO(6, 0xFF, 6, 0, 11, 0)
#define UART1_CTS_PC0 SIWX91X_GPIO(12, 0xFF, 9, 2, 0, 0)
#define UART1_CTS_PD3 SIWX91X_GPIO(9, 0xFF, 15, 3, 3, 0)
#define UART1_CTS_ULP1 SIWX91X_GPIO(9, 6, 23, 4, 1, 1)
#define UART1_CTS_ULP7 SIWX91X_GPIO(6, 6, 29, 4, 7, 7)
#define UART1_CTS_ULP9 SIWX91X_GPIO(9, 6, 31, 4, 9, 9)
#define UART1_RS485DE_PA9 SIWX91X_GPIO(6, 0xFF, 4, 0, 9, 0)
#define UART1_RS485DE_ULP2 SIWX91X_GPIO(6, 6, 24, 4, 2, 2)
#define UART1_RS485DE_ULP11 SIWX91X_GPIO(6, 6, 33, 4, 11, 11)
#define UART1_RS485EN_PA12 SIWX91X_GPIO(6, 0xFF, 7, 0, 12, 0)
#define UART1_RS485EN_PB10 SIWX91X_GPIO(6, 0xFF, 0, 1, 10, 0)
#define UART1_RS485EN_ULP0 SIWX91X_GPIO(6, 6, 22, 4, 0, 0)
#define UART1_RS485RE_PA8 SIWX91X_GPIO(6, 0xFF, 3, 0, 8, 0)
#define UART1_RS485RE_ULP1 SIWX91X_GPIO(6, 6, 23, 4, 1, 1)
#define UART1_RS485RE_ULP10 SIWX91X_GPIO(6, 6, 32, 4, 10, 10)
#define UART1_RTS_PA10 SIWX91X_GPIO(6, 0xFF, 5, 0, 10, 0)
#define UART1_RTS_PB11 SIWX91X_GPIO(6, 0xFF, 0, 1, 11, 0)
#define UART1_RTS_PB12 SIWX91X_GPIO(6, 0xFF, 0, 1, 12, 0)
#define UART1_RTS_PB15 SIWX91X_GPIO(12, 0xFF, 9, 1, 15, 0)
#define UART1_RTS_PD2 SIWX91X_GPIO(9, 0xFF, 14, 3, 2, 0)
#define UART1_RTS_ULP0 SIWX91X_GPIO(9, 6, 22, 4, 0, 0)
#define UART1_RTS_ULP6 SIWX91X_GPIO(6, 6, 28, 4, 6, 6)
#define UART1_RTS_ULP8 SIWX91X_GPIO(9, 6, 30, 4, 8, 8)
#define UART1_RX_PA6 SIWX91X_GPIO(6, 0xFF, 1, 0, 6, 0)
#define UART1_RX_PB13 SIWX91X_GPIO(6, 0xFF, 0, 1, 13, 0)
#define UART1_RX_PC1 SIWX91X_GPIO(12, 0xFF, 9, 2, 1, 0)
#define UART1_RX_ULP2 SIWX91X_GPIO(9, 6, 24, 4, 1, 1)
#define UART1_RX_ULP4 SIWX91X_GPIO(6, 6, 26, 4, 4, 4)
#define UART1_RX_ULP8 SIWX91X_GPIO(6, 6, 30, 4, 8, 8)
#define UART1_RX_ULP10 SIWX91X_GPIO(9, 6, 32, 4, 10, 10)
#define UART1_TX_PA15 SIWX91X_GPIO(2, 0xFF, 8, 0, 15, 0)
#define UART1_TX_PA7 SIWX91X_GPIO(6, 0xFF, 2, 0, 7, 0)
#define UART1_TX_PB14 SIWX91X_GPIO(6, 0xFF, 0, 1, 14, 0)
#define UART1_TX_PC2 SIWX91X_GPIO(12, 0xFF, 9, 2, 2, 0)
#define UART1_TX_ULP3 SIWX91X_GPIO(9, 6, 25, 4, 1, 1)
#define UART1_TX_ULP5 SIWX91X_GPIO(6, 6, 27, 4, 5, 5)
#define UART1_TX_ULP9 SIWX91X_GPIO(6, 6, 31, 4, 9, 9)
#define UART1_TX_ULP11 SIWX91X_GPIO(9, 6, 33, 4, 11, 11)
#define ULPI2C_SCL_PA11 SIWX91X_GPIO(9, 4, 6, 0, 11, 5)
#define ULPI2C_SCL_PA15 SIWX91X_GPIO(9, 4, 8, 0, 15, 7)