The power supply configuration is already set during
the early H7 soc init.
Let the clock initialization handle the voltage scaling.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Convert z_clock_hw_cycles_per_sec to unsigned int to increase
supported frequency range.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Enable support for HCLK, PCLK1, PCLK2, PCLK4 and PCLK5 as subsystem
clock sources identifiers on STM32N6 SoCs. HCLKx relates to the AHBx
buses clock and PCLKx relate to the APBx buses clocks.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove the inline attribute from stm32 clock drivers functions
especially for functions that are only referenced in the clock API
operation structure and therefore cannot be inline. As a generic
comment, today compiler are smart enough to optimize embedded software
without needing inline function attributes in the source files.
This change hopes that next stm32 clock driver will no more replicate
this bad habit when using existing source files as implementation
examples.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
IN_RANGE() macro from zephyr/sys/util.h returns a boolean value
so it should be treated as such and not compared to a decimal value.
Fix stm32 clock drivers accordingly and simplify places where the
value is compared to true.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct typo in STM32H7 HSI clock calibration directives introduced
in commit 6b167f2596 ("drivers: clock_control: add calibration for
h7 pllx_hsi") that currently has no functionnal impact but is worth
to be fixed for consistency.
No functional change,
Fixes: 6b167f2596
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove function exported stm32_system_clock_update() defined in
STM32H7RS series clock driver but that is not used and not even declared.
There already exists a CMSIS SystemCoreClockUpdate() function in
STM32 HAL drivers for the exact same purpose one may use if needed.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Currently, siwx917 have three instances of uart: ulpuart, uart1 and
uart2. However:
- The other drivers on siwx91x (i2c, dma, i2s, etc...) rather use
'ulp', '0' and '1'.
- The reference manual also uses 'ulp', '0' and '1'.
The source of the confusion probably come from the clock driver in
WiseConnect which use clocks USART1 and USART2. However, this probably
not expected.
So, this patch renames uart1 and uart2 in uart0 and uart1. This change
also impacts the names of pins and the names of the clocks.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Some of the CLOCK events are associated with features
not available on every nRF device.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
`watchdog_start_tick` is a just wrapper for `tick_start`.
To simplify, changing it to call directly.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add workaround to HFCLK start and stop in nrf54l. In future workaround
will be in nrfx driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add option to set the lowest DVFS operation point during initialization.
Option is by default enabled for nrf54h cores with DVFS.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Deprecate NRFS_LOCAL_DOMAIN_DVFS_SCALE_DOWN_AFTER_INIT option for
scaling down CPU frequency during dvfs handler initialization.
Clock control API is managing access to DVFS and DVFS should not
be controlled bypassing this API. Deprecated feature will be added in
the clock control.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Factorize STM32_CLOCK_*_GET() and STM32_MCO_CFGR_*_GET() macros
into a single series of STM32_DT_CLKSEL_*_GET() macros based on
recently introduced new common macros STM32_DT_CLKSEL_*_SHIFT and
STM32_DT_CLKSEL_*_MASK.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add Clock Control driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This driver is mostly the initial seed for further implementation of a
real clock driver.
It doesn't allow the user to choose the clock source for the various
peripherals. The driver hardcodes some sane values.
Note that for now, the driver snps,designware-i2c does not support
"clocks" attribute. So this patch hardcode the clock configuration in
the init of the clock driver.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
clean up usage of usage "#ifdef STM32_SRC_SYSCLK"
and code under the "#else" from clock_stm32_ll_common.c.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Some stm32f4, like the sm32f411 mcu have clk 48M on the main PLL output q
Some stm32f4, like the sm32f412 mcu have clk 48M on the PLL I2S output q
This PR is for selecting the right one
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Add a condition to check the clock supplying the CPU to match with
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
- Correct CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for EK-RA4W1
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Remove the LL_RCC_PLLI2S_ConfigDomain_48M for the stm32f4
w/o Q divider on the PLLI2S to configure the PLL48CK
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Check that the plli2s has a DIV-Q output or not. That depends
on the PLLi2S of some stm32F4xx devices
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes a multitude of Kconfigs that wrongly appear on devices
where support is literally impossible
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Makes the esp_console_init() calling during hardware initialization
conditioned to CONFIG_ESP_CONSOLE
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
When using synthesized low frequency clock, HFXO should be running
to ensure correct frequency.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
New events from nrfx_clock driver are not utilized for now
by the clock_control, so should be ignored to avoid assertion.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
