MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add hidden Kconfig option to Kconfig.cdc and allow
to configure CDC ACM UART device from devicetree.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
based on uart rom functions, also enable console driver
on top of this driver, which enables logging
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This is a follow-up to commit 3656ba5ae9.
Do not enforce pull-up resistors to be enabled on RXD and CTS pins
in nRF UART drivers, as in certain hardware designs this may be
undesirable or may even make certain hardware not working.
Instead, provide devicetree properties that allow enabling of those
resistors when it is actually needed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Add Atmel sam0 sercom[uart] pinctrl bindings and implements pinctrl at
driver level. It changes all sam0 boards to use new feature and remove
pinmux driver dependency for sercom[uart]. The samples that require a
binding were update to keep consistency and avoid errors.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Renesas has Serial Communication Interface with
FIFO (SCIF) hardware block which allow asynchronous and
synchronous serial communication. The SCIF has 16-stage FIFO
buffers separately for transmissions and reception.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add pinctrl-0 as being required on NXP Kinetis DTS bindings for I2C,
FTM, UART, and DSPI related devices.
Other devices like ethernet and CAN are utilized outside of just the
Kinetis family and thus we can not require pinctrl-0 property for them
at this time.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Automatic collision detection for half-duplex mode can be enabled
by setting `collision-detection` proprety for uart hardware
in the dts file. If the transmitted bit does not match the received
bit an error is raised. This is useful in RS-485 half-duplex mode.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Fixed the name of nodes in device-tree files by following rules:
If object is 'phandles', use underscores for object name.
If not, such as 'node' or 'property', use hyphens for object name.
This CL also applies normal style for all nodes in npcx device-tree
files.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
UARTs in Nordic devices only support a specified list of baud rates.
Choosing a different baud rate without this patch will cause a runtime
error, whereas with the constraint, this mistake is already found in
dts construction with a useful error message.
Signed-off-by: Peter Niebert <peter.niebert@univ-amu.fr>
ARM Server Base System Architecture defines Generic UART interface,
which is subset of PL011 UART.
Minimal SBSA UART implementation does not define UART hardware
configuration registers. Basically, only FIFOs and interrupt management
operation are defined.
Add SBSA mode to PL011 UART driver, so it can be used at SBSA-compatible
platforms, like Xen guest.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add some details to help new users learn how to manage the nodes
for compatibles corresponding to IP blocks on Nordic SoCs.
The focus is on IP blocks where the pinmux is configured in
devicetree. These typically have individual properties for each pin,
like a SCK pin on a SPI peripheral, which correspond directly to a
PSEL register value. These violate the usual devicetree convention of
using a 'foo-gpios <&gpioX ...>' phandle property and work in ways
that only make sense if you understand the underlying register map, so
it's worth explaining them a bit more carefully.
Skip these two bindings, which have no drivers: nordic,nrf-i2s.yaml,
nordic,nrf-pdm.yaml.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This adds support for the GRLIB APBUART UART peripheral commonly used in
LEON3/4/5 systems.
Driver features:
- Auto-detecting debug FIFO, if configured by GRMON
- Setting and getting UART transfer attributes
- Hardware FIFO if available
- Any number of APBUART devices based on devicetree
- Error status indication
- Polled operation
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
In fixing up the altera vendor prefix, we forgot to rename the binding
files to match the compatible.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There are a few cases in which "altera" was used instead of "altr" as
the vendor prefix. Update DTS and bindings in those cases to use "altr"
Fixes#29373
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have the driver default to UART_CFG_PARITY_NONE if no parity property
exists rather than using default in binding.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Instantiate RTT UART instances from devicetree nodes instead of from
Kconfig symbols. While RTT is implemented using software, not hardware,
it is emulating a hardware device, and thus should be configured through
devicetree. This allows the simulated UART device to be selected via
devicetree aliases and chosen nodes.
The following devicetree snippet will instantiate RTT channels 0 and 2
as UART devices.
```
/ {
rtt0: rtt_terminal {
compatible = "segger,rtt-uart";
label = "rtt_terminal";
status = "okay";
};
rtt2: rtt_secondary {
compatible = "segger,rtt-uart";
label = "rtt_app_specific";
status = "okay";
};
};
```
Fixes the RTT portion of #10621.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This CL configures the UART wake-up event triggered from a falling edge
(START condition) on CR_SIN pin. It also includes:
1. Introduce wui_maps property in yaml file to present relationship
between Wake-Up Input (WUI) and UART device.
2. Implement wake-up mechanism by MIWU api functions.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Added support for hardware flow control in EFM32 UART driver.
Signed-off-by: Timo Dammes <timo.dammes@lemonbeat.com>
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Add IUART driver based on MCUX SDK. This driver is used to provide
serial console support on i.MX8M Mini SoC.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Cleaned up flow control configuration. Added support for using only
cts or only rts.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Adding port information for uart tx and rx pins in dts, so that it can
be more systematically retrieved in the uart driver.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-uart binding for dma to replace the rxdma and txdma
properties with proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the GCLK, MCLK, and PM clock controllers. Add bindings
and devicetree nodes associated with these clock controllers. Also add
clock references for the SERCOM peripheral set to allow those drivers
(i2c, spi, uart) to utilize this information.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctl support for the SAM UART and SAM USART devices. We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The flexcomm peripheral on lpc socs can be configured into uart, spi,
i2c, or i2s mode. Introduce a shared device tree binding that gets
included by the more specific driver type bindings.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Extended nrf_uart driver to support TX only.
When RX pin is not provided then RX is not started at all. This
allows to achieve low power with logging/console enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Extended nrf_uarte driver to support TX only UARTE instances.
When RX pin is not provided then RX is not started at all. This
allows to achieve low power with logging/console enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add any useful information from 'title:' to the 'description:' strings
(e.g. explanations of acronyms), and remove 'title:' as well as any
copy-pasted "this binding gives a ..." boilerplate.
Also clean some description strings up a bit.
Some other things could probably be cleaned up (replacing 'GPIO node'
with 'GPIO controller' on controllers for consistency, for example), but
I kept things close to the original to avoid accidentally messing up.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
