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dts: atmel: sam0: Add initial clock devicetree support

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Add support for the GCLK, MCLK, and PM clock controllers.  Add bindings
and devicetree nodes associated with these clock controllers.  Also add
clock references for the SERCOM peripheral set to allow those drivers
(i2c, spi, uart) to utilize this information.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-20 14:49:12 -05:00 committed by Kumar Gala
parent d873573f76
commit 8357005ba1
13 changed files with 172 additions and 0 deletions
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12
dts/arm/atmel/samd20.dtsi
View File

@ -39,26 +39,38 @@
&sercom0 {
interrupts = <7 0>;
clocks = <&gclk 0xd>, <&pm 0x20 2>;
clock-names = "GCLK", "PM";
};
&sercom1 {
interrupts = <8 0>;
clocks = <&gclk 0xe>, <&pm 0x20 3>;
clock-names = "GCLK", "PM";
};
&sercom2 {
interrupts = <9 0>;
clocks = <&gclk 0xf>, <&pm 0x20 4>;
clock-names = "GCLK", "PM";
};
&sercom3 {
interrupts = <10 0>;
clocks = <&gclk 0x10>, <&pm 0x20 5>;
clock-names = "GCLK", "PM";
};
&sercom4 {
interrupts = <11 0>;
clocks = <&gclk 0x11>, <&pm 0x20 6>;
clock-names = "GCLK", "PM";
};
&sercom5 {
interrupts = <12 0>;
clocks = <&gclk 0x12>, <&pm 0x20 7>;
clock-names = "GCLK", "PM";
};
&tc4 {

12
dts/arm/atmel/samd21.dtsi
View File

@ -39,26 +39,38 @@
&sercom0 {
interrupts = <9 0>;
clocks = <&gclk 0x14>, <&pm 0x20 2>;
clock-names = "GCLK", "PM";
};
&sercom1 {
interrupts = <10 0>;
clocks = <&gclk 0x15>, <&pm 0x20 3>;
clock-names = "GCLK", "PM";
};
&sercom2 {
interrupts = <11 0>;
clocks = <&gclk 0x16>, <&pm 0x20 4>;
clock-names = "GCLK", "PM";
};
&sercom3 {
interrupts = <12 0>;
clocks = <&gclk 0x17>, <&pm 0x20 5>;
clock-names = "GCLK", "PM";
};
&sercom4 {
interrupts = <13 0>;
clocks = <&gclk 0x18>, <&pm 0x20 6>;
clock-names = "GCLK", "PM";
};
&sercom5 {
interrupts = <14 0>;
clocks = <&gclk 0x19>, <&pm 0x20 7>;
clock-names = "GCLK", "PM";
};
&tc4 {

13
dts/arm/atmel/samd2x.dtsi
View File

@ -73,6 +73,19 @@
};
};
pm: pm@40000400 {
compatible = "atmel,samd2x-pm";
reg = <0x40000400 0x400>;
interrupts = <0 0>;
#clock-cells = <2>;
};
gclk: gclk@40000c00 {
compatible = "atmel,samd2x-gclk";
reg = <0x40000c00 0x400>;
#clock-cells = <1>;
};
eic: eic@40001800 {
compatible = "atmel,sam0-eic";
reg = <0x40001800 0x1C>;

28
dts/arm/atmel/samd5x.dtsi
View File

@ -72,6 +72,18 @@
<0x00806018 0x4>;
};
mclk: mclk@40000800 {
compatible = "atmel,samd5x-mclk";
reg = <0x40000800 0x400>;
#clock-cells = <2>;
};
gclk: gclk@40001c00 {
compatible = "atmel,samd5x-gclk";
reg = <0x40001c00 0x400>;
#clock-cells = <1>;
};
nvmctrl: nvmctrl@41004000 {
compatible = "atmel,sam0-nvmctrl";
label = "FLASH_CTRL";
@ -143,6 +155,8 @@
interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
status = "disabled";
label = "SERCOM0";
clocks = <&gclk 7>, <&mclk 0x14 12>;
clock-names = "GCLK", "MCLK";
};
sercom1: sercom@40003400 {
@ -151,6 +165,8 @@
interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
status = "disabled";
label = "SERCOM1";
clocks = <&gclk 8>, <&mclk 0x14 13>;
clock-names = "GCLK", "MCLK";
};
sercom2: sercom@41012000 {
@ -159,6 +175,8 @@
interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
status = "disabled";
label = "SERCOM2";
clocks = <&gclk 23>, <&mclk 0x18 9>;
clock-names = "GCLK", "MCLK";
};
sercom3: sercom@41014000 {
@ -167,6 +185,8 @@
interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
status = "disabled";
label = "SERCOM3";
clocks = <&gclk 24>, <&mclk 0x18 10>;
clock-names = "GCLK", "MCLK";
};
sercom4: sercom@43000000 {
@ -175,6 +195,8 @@
interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
status = "disabled";
label = "SERCOM4";
clocks = <&gclk 34>, <&mclk 0x20 0>;
clock-names = "GCLK", "MCLK";
};
sercom5: sercom@43000400 {
@ -183,6 +205,8 @@
interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
status = "disabled";
label = "SERCOM5";
clocks = <&gclk 35>, <&mclk 0x20 1>;
clock-names = "GCLK", "MCLK";
};
sercom6: sercom@43000800 {
@ -191,6 +215,8 @@
interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
status = "disabled";
label = "SERCOM6";
clocks = <&gclk 36>, <&mclk 0x20 2>;
clock-names = "GCLK", "MCLK";
};
sercom7: sercom@43000C00 {
@ -199,6 +225,8 @@
interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
status = "disabled";
label = "SERCOM7";
clocks = <&gclk 37>, <&mclk 0x20 3>;
clock-names = "GCLK", "MCLK";
};
porta: gpio@41008000 {

12
dts/arm/atmel/samr21.dtsi
View File

@ -47,26 +47,38 @@
&sercom0 {
interrupts = <9 0>;
clocks = <&gclk 0x14>, <&pm 0x20 2>;
clock-names = "GCLK", "PM";
};
&sercom1 {
interrupts = <10 0>;
clocks = <&gclk 0x15>, <&pm 0x20 3>;
clock-names = "GCLK", "PM";
};
&sercom2 {
interrupts = <11 0>;
clocks = <&gclk 0x16>, <&pm 0x20 4>;
clock-names = "GCLK", "PM";
};
&sercom3 {
interrupts = <12 0>;
clocks = <&gclk 0x17>, <&pm 0x20 5>;
clock-names = "GCLK", "PM";
};
&sercom4 {
interrupts = <13 0>;
clocks = <&gclk 0x18>, <&pm 0x20 6>;
clock-names = "GCLK", "PM";
};
&sercom5 {
interrupts = <14 0>;
clocks = <&gclk 0x19>, <&pm 0x20 7>;
clock-names = "GCLK", "PM";
};
&tc4 {

3
dts/bindings/arm/atmel,sam0-sercom.yaml
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@ -10,3 +10,6 @@ properties:
interrupts:
required: true
clocks:
required: true

19
dts/bindings/arm/atmel,samd2x-pm.yaml Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD2x Power Manger (PM)
compatible: "atmel,samd2x-pm"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-cells:
- offset
- bit

18
dts/bindings/clock/atmel,samd2x-gclk.yaml Normal file
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@ -0,0 +1,18 @@
# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD2x Generic Clock Controller (GCLK)
compatible: "atmel,samd2x-gclk"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 1
clock-cells:
- clkctrl_id

18
dts/bindings/clock/atmel,samd5x-gclk.yaml Normal file
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@ -0,0 +1,18 @@
# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD5x Generic Clock Controller (GCLK)
compatible: "atmel,samd5x-gclk"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 1
clock-cells:
- periph_ch

19
dts/bindings/clock/atmel,samd5x-mclk.yaml Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD5x Generic Clock Controller (MCLK)
compatible: "atmel,samd5x-mclk"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-cells:
- offset
- bit

6
dts/bindings/i2c/atmel,sam0-i2c.yaml
View File

@ -14,6 +14,12 @@ properties:
interrupts:
required: true
clocks:
required: true
clock-names:
required: true
dma:
type: int
required: false

6
dts/bindings/serial/atmel,sam0-uart.yaml
View File

@ -11,6 +11,12 @@ properties:
interrupts:
required: true
clocks:
required: true
clock-names:
required: true
rxpo:
type: int
required: true

6
dts/bindings/spi/atmel,sam0-spi.yaml
View File

@ -11,6 +11,12 @@ properties:
reg:
required: true
clocks:
required: true
clock-names:
required: true
dipo:
type: int
required: true