From 8357005ba12f2a10d080d7bd40405c4e796c77cf Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 20 Apr 2020 14:49:12 -0500 Subject: [PATCH] dts: atmel: sam0: Add initial clock devicetree support Add support for the GCLK, MCLK, and PM clock controllers. Add bindings and devicetree nodes associated with these clock controllers. Also add clock references for the SERCOM peripheral set to allow those drivers (i2c, spi, uart) to utilize this information. Signed-off-by: Kumar Gala --- dts/arm/atmel/samd20.dtsi | 12 ++++++++++ dts/arm/atmel/samd21.dtsi | 12 ++++++++++ dts/arm/atmel/samd2x.dtsi | 13 +++++++++++ dts/arm/atmel/samd5x.dtsi | 28 +++++++++++++++++++++++ dts/arm/atmel/samr21.dtsi | 12 ++++++++++ dts/bindings/arm/atmel,sam0-sercom.yaml | 3 +++ dts/bindings/arm/atmel,samd2x-pm.yaml | 19 +++++++++++++++ dts/bindings/clock/atmel,samd2x-gclk.yaml | 18 +++++++++++++++ dts/bindings/clock/atmel,samd5x-gclk.yaml | 18 +++++++++++++++ dts/bindings/clock/atmel,samd5x-mclk.yaml | 19 +++++++++++++++ dts/bindings/i2c/atmel,sam0-i2c.yaml | 6 +++++ dts/bindings/serial/atmel,sam0-uart.yaml | 6 +++++ dts/bindings/spi/atmel,sam0-spi.yaml | 6 +++++ 13 files changed, 172 insertions(+) create mode 100644 dts/bindings/arm/atmel,samd2x-pm.yaml create mode 100644 dts/bindings/clock/atmel,samd2x-gclk.yaml create mode 100644 dts/bindings/clock/atmel,samd5x-gclk.yaml create mode 100644 dts/bindings/clock/atmel,samd5x-mclk.yaml diff --git a/dts/arm/atmel/samd20.dtsi b/dts/arm/atmel/samd20.dtsi index a2adca6d1f9..cd0498c9549 100644 --- a/dts/arm/atmel/samd20.dtsi +++ b/dts/arm/atmel/samd20.dtsi @@ -39,26 +39,38 @@ &sercom0 { interrupts = <7 0>; + clocks = <&gclk 0xd>, <&pm 0x20 2>; + clock-names = "GCLK", "PM"; }; &sercom1 { interrupts = <8 0>; + clocks = <&gclk 0xe>, <&pm 0x20 3>; + clock-names = "GCLK", "PM"; }; &sercom2 { interrupts = <9 0>; + clocks = <&gclk 0xf>, <&pm 0x20 4>; + clock-names = "GCLK", "PM"; }; &sercom3 { interrupts = <10 0>; + clocks = <&gclk 0x10>, <&pm 0x20 5>; + clock-names = "GCLK", "PM"; }; &sercom4 { interrupts = <11 0>; + clocks = <&gclk 0x11>, <&pm 0x20 6>; + clock-names = "GCLK", "PM"; }; &sercom5 { interrupts = <12 0>; + clocks = <&gclk 0x12>, <&pm 0x20 7>; + clock-names = "GCLK", "PM"; }; &tc4 { diff --git a/dts/arm/atmel/samd21.dtsi b/dts/arm/atmel/samd21.dtsi index 9d1382288a9..fa874397c46 100644 --- a/dts/arm/atmel/samd21.dtsi +++ b/dts/arm/atmel/samd21.dtsi @@ -39,26 +39,38 @@ &sercom0 { interrupts = <9 0>; + clocks = <&gclk 0x14>, <&pm 0x20 2>; + clock-names = "GCLK", "PM"; }; &sercom1 { interrupts = <10 0>; + clocks = <&gclk 0x15>, <&pm 0x20 3>; + clock-names = "GCLK", "PM"; }; &sercom2 { interrupts = <11 0>; + clocks = <&gclk 0x16>, <&pm 0x20 4>; + clock-names = "GCLK", "PM"; }; &sercom3 { interrupts = <12 0>; + clocks = <&gclk 0x17>, <&pm 0x20 5>; + clock-names = "GCLK", "PM"; }; &sercom4 { interrupts = <13 0>; + clocks = <&gclk 0x18>, <&pm 0x20 6>; + clock-names = "GCLK", "PM"; }; &sercom5 { interrupts = <14 0>; + clocks = <&gclk 0x19>, <&pm 0x20 7>; + clock-names = "GCLK", "PM"; }; &tc4 { diff --git a/dts/arm/atmel/samd2x.dtsi b/dts/arm/atmel/samd2x.dtsi index 8b537304bc4..7ee613a22e6 100644 --- a/dts/arm/atmel/samd2x.dtsi +++ b/dts/arm/atmel/samd2x.dtsi @@ -73,6 +73,19 @@ }; }; + pm: pm@40000400 { + compatible = "atmel,samd2x-pm"; + reg = <0x40000400 0x400>; + interrupts = <0 0>; + #clock-cells = <2>; + }; + + gclk: gclk@40000c00 { + compatible = "atmel,samd2x-gclk"; + reg = <0x40000c00 0x400>; + #clock-cells = <1>; + }; + eic: eic@40001800 { compatible = "atmel,sam0-eic"; reg = <0x40001800 0x1C>; diff --git a/dts/arm/atmel/samd5x.dtsi b/dts/arm/atmel/samd5x.dtsi index d264a399754..1e29ed2720e 100644 --- a/dts/arm/atmel/samd5x.dtsi +++ b/dts/arm/atmel/samd5x.dtsi @@ -72,6 +72,18 @@ <0x00806018 0x4>; }; + mclk: mclk@40000800 { + compatible = "atmel,samd5x-mclk"; + reg = <0x40000800 0x400>; + #clock-cells = <2>; + }; + + gclk: gclk@40001c00 { + compatible = "atmel,samd5x-gclk"; + reg = <0x40001c00 0x400>; + #clock-cells = <1>; + }; + nvmctrl: nvmctrl@41004000 { compatible = "atmel,sam0-nvmctrl"; label = "FLASH_CTRL"; @@ -143,6 +155,8 @@ interrupts = <46 0>, <47 0>, <48 0>, <49 0>; status = "disabled"; label = "SERCOM0"; + clocks = <&gclk 7>, <&mclk 0x14 12>; + clock-names = "GCLK", "MCLK"; }; sercom1: sercom@40003400 { @@ -151,6 +165,8 @@ interrupts = <50 0>, <51 0>, <52 0>, <53 0>; status = "disabled"; label = "SERCOM1"; + clocks = <&gclk 8>, <&mclk 0x14 13>; + clock-names = "GCLK", "MCLK"; }; sercom2: sercom@41012000 { @@ -159,6 +175,8 @@ interrupts = <54 0>, <55 0>, <56 0>, <57 0>; status = "disabled"; label = "SERCOM2"; + clocks = <&gclk 23>, <&mclk 0x18 9>; + clock-names = "GCLK", "MCLK"; }; sercom3: sercom@41014000 { @@ -167,6 +185,8 @@ interrupts = <58 0>, <59 0>, <60 0>, <61 0>; status = "disabled"; label = "SERCOM3"; + clocks = <&gclk 24>, <&mclk 0x18 10>; + clock-names = "GCLK", "MCLK"; }; sercom4: sercom@43000000 { @@ -175,6 +195,8 @@ interrupts = <62 0>, <63 0>, <64 0>, <65 0>; status = "disabled"; label = "SERCOM4"; + clocks = <&gclk 34>, <&mclk 0x20 0>; + clock-names = "GCLK", "MCLK"; }; sercom5: sercom@43000400 { @@ -183,6 +205,8 @@ interrupts = <66 0>, <67 0>, <68 0>, <69 0>; status = "disabled"; label = "SERCOM5"; + clocks = <&gclk 35>, <&mclk 0x20 1>; + clock-names = "GCLK", "MCLK"; }; sercom6: sercom@43000800 { @@ -191,6 +215,8 @@ interrupts = <70 0>, <71 0>, <72 0>, <73 0>; status = "disabled"; label = "SERCOM6"; + clocks = <&gclk 36>, <&mclk 0x20 2>; + clock-names = "GCLK", "MCLK"; }; sercom7: sercom@43000C00 { @@ -199,6 +225,8 @@ interrupts = <74 0>, <75 0>, <76 0>, <77 0>; status = "disabled"; label = "SERCOM7"; + clocks = <&gclk 37>, <&mclk 0x20 3>; + clock-names = "GCLK", "MCLK"; }; porta: gpio@41008000 { diff --git a/dts/arm/atmel/samr21.dtsi b/dts/arm/atmel/samr21.dtsi index 247c69071c3..a17a87a2ba6 100644 --- a/dts/arm/atmel/samr21.dtsi +++ b/dts/arm/atmel/samr21.dtsi @@ -47,26 +47,38 @@ &sercom0 { interrupts = <9 0>; + clocks = <&gclk 0x14>, <&pm 0x20 2>; + clock-names = "GCLK", "PM"; }; &sercom1 { interrupts = <10 0>; + clocks = <&gclk 0x15>, <&pm 0x20 3>; + clock-names = "GCLK", "PM"; }; &sercom2 { interrupts = <11 0>; + clocks = <&gclk 0x16>, <&pm 0x20 4>; + clock-names = "GCLK", "PM"; }; &sercom3 { interrupts = <12 0>; + clocks = <&gclk 0x17>, <&pm 0x20 5>; + clock-names = "GCLK", "PM"; }; &sercom4 { interrupts = <13 0>; + clocks = <&gclk 0x18>, <&pm 0x20 6>; + clock-names = "GCLK", "PM"; }; &sercom5 { interrupts = <14 0>; + clocks = <&gclk 0x19>, <&pm 0x20 7>; + clock-names = "GCLK", "PM"; }; &tc4 { diff --git a/dts/bindings/arm/atmel,sam0-sercom.yaml b/dts/bindings/arm/atmel,sam0-sercom.yaml index b183af079b5..448a4f7d7e0 100644 --- a/dts/bindings/arm/atmel,sam0-sercom.yaml +++ b/dts/bindings/arm/atmel,sam0-sercom.yaml @@ -10,3 +10,6 @@ properties: interrupts: required: true + + clocks: + required: true diff --git a/dts/bindings/arm/atmel,samd2x-pm.yaml b/dts/bindings/arm/atmel,samd2x-pm.yaml new file mode 100644 index 00000000000..88af94202cf --- /dev/null +++ b/dts/bindings/arm/atmel,samd2x-pm.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2020, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAMD2x Power Manger (PM) + +compatible: "atmel,samd2x-pm" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 2 + +clock-cells: + - offset + - bit diff --git a/dts/bindings/clock/atmel,samd2x-gclk.yaml b/dts/bindings/clock/atmel,samd2x-gclk.yaml new file mode 100644 index 00000000000..29cce3b5984 --- /dev/null +++ b/dts/bindings/clock/atmel,samd2x-gclk.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2020, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAMD2x Generic Clock Controller (GCLK) + +compatible: "atmel,samd2x-gclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 1 + +clock-cells: + - clkctrl_id diff --git a/dts/bindings/clock/atmel,samd5x-gclk.yaml b/dts/bindings/clock/atmel,samd5x-gclk.yaml new file mode 100644 index 00000000000..65a9cadc551 --- /dev/null +++ b/dts/bindings/clock/atmel,samd5x-gclk.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2020, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAMD5x Generic Clock Controller (GCLK) + +compatible: "atmel,samd5x-gclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 1 + +clock-cells: + - periph_ch diff --git a/dts/bindings/clock/atmel,samd5x-mclk.yaml b/dts/bindings/clock/atmel,samd5x-mclk.yaml new file mode 100644 index 00000000000..53b1ce93c05 --- /dev/null +++ b/dts/bindings/clock/atmel,samd5x-mclk.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2020, Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAMD5x Generic Clock Controller (MCLK) + +compatible: "atmel,samd5x-mclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 2 + +clock-cells: + - offset + - bit diff --git a/dts/bindings/i2c/atmel,sam0-i2c.yaml b/dts/bindings/i2c/atmel,sam0-i2c.yaml index a815cc3beab..01b0d1b1e88 100644 --- a/dts/bindings/i2c/atmel,sam0-i2c.yaml +++ b/dts/bindings/i2c/atmel,sam0-i2c.yaml @@ -14,6 +14,12 @@ properties: interrupts: required: true + clocks: + required: true + + clock-names: + required: true + dma: type: int required: false diff --git a/dts/bindings/serial/atmel,sam0-uart.yaml b/dts/bindings/serial/atmel,sam0-uart.yaml index f50fa726189..9957a009a72 100644 --- a/dts/bindings/serial/atmel,sam0-uart.yaml +++ b/dts/bindings/serial/atmel,sam0-uart.yaml @@ -11,6 +11,12 @@ properties: interrupts: required: true + clocks: + required: true + + clock-names: + required: true + rxpo: type: int required: true diff --git a/dts/bindings/spi/atmel,sam0-spi.yaml b/dts/bindings/spi/atmel,sam0-spi.yaml index bc69a84429e..74356a6eef1 100644 --- a/dts/bindings/spi/atmel,sam0-spi.yaml +++ b/dts/bindings/spi/atmel,sam0-spi.yaml @@ -11,6 +11,12 @@ properties: reg: required: true + clocks: + required: true + + clock-names: + required: true + dipo: type: int required: true