Remove the support of the Nucleo WBA52CG board since it is NRND
(Not Recommended for New Design) and it is not supported anymore
in the STM32CubeWBA from version 1.1.0 (July 2023).
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add some overlay files for the silabs xg29_rb4412a board to enable tests
on the board. Also add the platform to some testcase.yaml files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The UART test for USART needs to move the console to an EUSART instance
in order to free up USART0 for the test. Since EUSART1 is configured for
SPI use by the board DTS, use EUSART0 for console.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit disables CONFIG_TEST_USERSPACE in
intel_rpl_s_crb.conf of uart_async_api
testcase.Enabling this config introduces
restrictions that interfere with cacheable
regions by blocking access and modifying
cache attributes.By disabling this
configuration, the following issues
are resolved:
-Cacheable region retain their attributes.
-Execution and data transactions work without
restrictions.
-System behavior align with expected
configuration in privileged mode.
-Some code primarily relying on non-cache
region continues to work.
This change is neccessary to ensure
cachebale memory regions function as intended
without interferance from user mode restrictions.
Signed-off-by: S Swetha <s.swetha@intel.com>
Add UART test overlays for Nucleo N657x0-Q and STM32N6570 DK boards.
Remove non serial boot conf file since they are now unnecessary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add new target to the following tests:
- uart_elementary
- uart_async_api
- uart_mix_fifo_poll
- uart_pm
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Due to cm7 on RT1180 is secondary core, and dtcm have been used
as sram directly, so there is no need to define zephyr,dtcm node.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Enable device runtime PM for nrf54h20dk/nrf54h20/cpuapp where
fast UARTE (uart120) is tested.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Convert qspi and hyperflash to variants instead of revisions by popular
demand.
And convert evkb into a revision instead of a different board.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Deprecate mode which is using TIMER+(D)PPI for reliable byte counting.
Recently a new approach is added (CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
which supports reliable byte counting without additional HW resource.
This mode is planned to be the only supported RX path mode.
Enhanced RX has slightly different behavior. There are no partial RX
packets (events with non-zero offset). There is UART_RX_BUF_RELEASED
after each UART_RX_RDY event.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Enable this test in the simulated nrf54l15 by providing
an appropriate overlay.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add second instance to be tested on nrf54h20dk. uart120 is a fast UARTE
which works on fixed pin locations. It is not available for cpuppr core.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Enable this test in the simulated nrf5340 by providing
an appropriate overlay.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
nrf54h20dk_nrf54h20_cpurad by default has less RAM dedicated for
DMA transfers and default 1k buffer cannot be used for
uart_async_long_buf case. Use custom value.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Updated overlay files to test using nocache.
and run outside of usersapce mode to avoid
inaccessible memory regions when using nocache on RT parts.
Also updated testcase file to reflect nocache testing.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
