Commit Graph

371 Commits

Author SHA1 Message Date
Sylvio Alves
e0a915a178 soc: espressif: convert rtc peripheral to clock subsystem
Current ESP32 clock system is mixed with RTC labeling/registers,
but it doesn't implement a real-time clock (RTC) driver.

To avoid confusion and allow adding a proper RTC driver later,
this commit renames the existing RTC interface to CLOCK and make
it as a subsystem without any peripheral attached to it.

This better reflects its actual purpose as a general clock controller.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-06-02 17:38:08 +02:00
Joel Guittet
9d4530fb79 drivers: counter: introduce counter node in esp32 timers
Add counter device tree node to the esp32 timers.

Signed-off-by: Joel Guittet <joelguittet@gmail.com>
2025-05-29 08:41:59 +02:00
Vit Stanicek
cb1a7df652 dts: xtensa: Add DT for SoC mimxrt685s/hifi4
Add DT for the mimxrt685s/hifi4 SoC (i.MX RT685's HiFi 4 DSP core).

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-05-21 20:11:19 +02:00
Adrian Bonislawski
9c2983926a dts: intel_adsp_ace30: merge and cleanup ace30 dtsi files
The new ace30 files structure is organized as follows:

intel_adsp_ace30.dtsi - main file for all variants
intel_adsp_ace30_ptl.dtsi - additional file for PTL variant
intel_adsp_ace30_wcl.dtsi - additional file for WCL variant

The main ace30.dtsi file contains most of the fields,
with only the differences specified in the ace30_ptl.dtsi
and ace30_wcl.dtsi files.

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-05-15 22:14:44 +02:00
Adrian Bonislawski
7918839ddd intel_adsp: ace30: Bring up ACE 3.0 (WCL)
This commit adds definition of ACE 3.0 Wildcat Lake board

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-05-15 22:14:44 +02:00
Tomasz Leman
dbf1d54ddd dts: update power-states node for ACE 3.0
This patch modifies the DTS files for Intel ADSP ACE 3.0 platforms,
ensuring the power-states node is a child of the cpus node. This change
aligns with Linux conventions and mirrors the adjustments made in commit
e4c43e4cc9 for other platforms.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2025-05-07 15:11:02 +02:00
Iuliana Prodan
66ab75ff96 dts: xtensa: nxp: add mailbox node
Add mailbox node used for inter-process communication.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2025-04-07 15:17:34 +02:00
Iuliana Prodan
54f99bf8b0 dts: xtensa: nxp: fix compile warning
Fix the following compile warning:
"Warning (unique_unit_address_if_enabled):
/cpus/cpu@0: duplicate unit-address (also used
in node /cpus/interrupt-controller@0)"

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2025-04-07 15:17:34 +02:00
Marcio Ribeiro
c01489dadc drivers: i2s: esp32: add support for non-gdma SoCs
Adds support for:
- esp32
- esp32s2

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-04-06 12:17:58 +02:00
Iuliana Prodan
d03c02a75e dts: xtensa: nxp: Add device tree for HiFi1 core from NXP i.MXRT700
Add a basic device tree for the HiFi1 DSP from NXP i.MXRT700.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2025-03-07 19:42:36 +01:00
Iuliana Prodan
3b32e697ab dts: xtensa: nxp: Add device tree for HiFi4 core from NXP i.MXRT700
Add a basic device tree for the HiFi4 DSP from NXP i.MXRT700.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2025-03-07 19:42:36 +01:00
Marek Matej
d13fae97e4 soc: espressif: Fix psram0 node size and smh heap size calculation
Fixing multiple things related to psram usage:
- fix conflicting psram0 dts node for all ESP32 SiP and SoC.
- fix dcache and icache area used in psram mapping.
- fix smh spiram heap allocations.
- add `espressif,esp32-psram` compatible to set psram0 size in dts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-02-25 07:56:19 +01:00
Adrian Bonislawski
72f820cda3 dts: xtensa: intel_adsp_ace30: enable Mic privacy driver
Enable Microphone Privacy driver for Intel ACE 3.0 platform

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-02-13 01:13:31 +01:00
Marek Matej
c9849c1d24 dts: esp32s3: add cache node to common dtsi
Create the cache memory node instead of hardcoding addresses.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-02-12 20:25:48 +01:00
Daniel Baluta
aaa119d757 dts: xtensa: nxp_imx8m: Add PDM MICFIL node
This adds micfil node for NPX i.MX8MP SOC.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2025-02-08 00:32:26 +01:00
Raffael Rostagno
5ee8600a59 drivers: adc: esp32: Clock init
Peripheral clock init.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-01-27 17:08:30 +01:00
Taeyoun Park
9769a39766 dts: xtensa: Fix gpio-reserved-ranges of gpio1
The range of GPIO37-38 is <5 2>

Signed-off-by: Taeyoun Park <typark0422@pethcare.com>
2024-12-26 15:31:43 +01:00
Daniel Baluta
020985b38b dts: xtensa: nxp_imx8m: Add SAI3 and SDMA3 node
Add sai3 and sdma3 nodes found on NXP i.MX8MP SOC.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2024-12-23 17:11:09 +01:00
Raffael Rostagno
4f61ce738b dts: soc: esp32: Counter driver update
Add clocks field to dts for clock control.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-12-17 15:23:38 +01:00
Iuliana Prodan
d9caf60add dts: xtensa: nxp: imx8ulp: fix sram address
Fix addresses for sram0 and sram1.

Fixes: a7b7364c4e ("dts/xtensa/nxp: Add dtsi for imx8ulp")
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2024-12-17 11:38:06 +00:00
Laurentiu Mihalcea
3651725316 dts: xtensa: nxp_imx8: add edma power domains
Add power domains for EDMA0's channels 6, 7, 14, and 15.
For QM these are identified as IMX_SC_R_DMA_2_*, while
for QXP thy are identified as IMX_SC_R_DMA_0_*.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-12-13 20:05:00 +01:00
Laurentiu Mihalcea
2eecf88698 dts: xtensa: nxp_imx8: move up the definition of system-controller
This has no address space and doesn't belong between peripheral
nodes. Move it up the DTSI for better visibility. No functional
change.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-12-13 20:05:00 +01:00
Laurentiu Mihalcea
c8a984708c dts: xtensa: add imx8qm and imx8qxp DTSI variants
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.

One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:

"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"

To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-12-13 20:05:00 +01:00
Marek Matej
a7a05b9e7f dts: espressif: Update AMP sram nodes for ESP32 and ESP32-S3
Set AMP dts nodes (ipm, mbox, ...) to use fixed locations in reserved
memory areas. Those areas memories are delimited in the `memory.h`.
Size of the occupied areas can be calculated but the dts nodes addresses
needs to be set manually in every case.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-12 11:38:22 +01:00
Tomasz Leman
fe2861b5cd dai: intel: ssp: Refactor power management initialization
This patch refactors the power management initialization for the SSP
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:

1. Replacing the conditional initialization of power management state
   with a call to `pm_device_driver_init` in the `ssp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the SSP nodes
   in the device tree files for ACE15, ACE20, and ACE30.
3. Moving the power domain assignment for the SSP device in the device
   tree. The previous configuration resulted in the device not being under
   any power domain and being initialized as always ON.

These changes ensure that the SSP driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-12-11 21:34:57 +01:00
Tomasz Leman
618e83e721 dai: intel: dmic: Refactor power management initialization
This patch refactors the power management initialization for the DMIC
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:

1. Replacing the conditional initialization of power management state
   with a call to `pm_device_driver_init` in the
   `dai_dmic_initialize_device` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the DMIC nodes
   in the device tree files for ACE15, ACE20, and ACE30.

These changes ensure that the DMIC driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-12-11 21:34:57 +01:00
Tomasz Leman
329675ab7c dma: intel_adsp_hda: Refactor power management and correct power domains
This patch addresses several issues with the Intel ADSP HDA DMA driver:

1. Refactors the HDA DMA power management initialization. The previous
   use of `pm_device_runtime_enable` was incorrect. The updated approach
   relies on enabling runtime power management through the device tree
   using the `zephyr,pm-device-runtime-auto` property. Additionally, the
   patch removes redundant device initialization steps as these are already
   handled by `pm_device_driver_init` when the device is under a power
   domain.

2. Corrects the power domain assignment for the HDA link. The HDA link
   was previously assigned to the io0 power domain based on a
   misinterpretation of the documentation. The correct power domain
   assignment is now based on updated documentation for LNL, ensuring that
   the HDA link is associated with the appropriate power domain.

These changes ensure that the HDA DMA driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the correct power domains are used.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-12-11 21:34:35 +01:00
Tomasz Leman
fd4a4bf702 dai: intel: hda: Add power management
This patch addresses the following issues with the Intel HDA DAI driver:

1. Adds power management support for the HDA DAI driver by implementing
   the `hda_pm_action` function and integrating it with the Zephyr power
   management framework.
2. Ensures balanced calls to `pm_device_runtime_get` and
   `pm_device_runtime_put` by modifying the `probe` and `remove`
   functions to use these power management calls.
3. Ensures that the io0 power domain is active when the HD Audio is in
   use by assigning the correct power domain to the HDA DAI devices in
   the device tree files for various Intel ADSP platforms (ace15_mtpm,
   ace20_lnl, ace30, ace30_ptl).
4. Enables runtime power management for the HDA DAI devices by adding
   the `zephyr,pm-device-runtime-auto` property in the device tree.

These changes ensure that the HDA DAI driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the io0 power domain is active when required.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-12-11 21:34:35 +01:00
Manuel Argüelles
f85f8ee88e dts: bindings: rename nxp,kinetis-lpuart compatible
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-12-11 08:00:30 +01:00
Marcio Ribeiro
98277c9889 dts: esp32: enhance memory regions description
Add regions to .dtsi files to better describe SoCs memory

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-07 11:02:46 +01:00
Sylvio Alves
198f9907e2 dtsi: espressif: add missing address-cell entries
Add address-cell field into interrupt allocator entry
to overcome build warnings.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-11-27 10:38:44 -05:00
Marek Matej
78c1def4db boards: esp32xx: Use common partition tables
* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-11-22 17:45:24 +01:00
DineshKumar Kalva
173cc387a0 soc: amd: acp_6_0: add support for AMD ACP_6_0 soc.
Add a common part for AMD board ACP_6_0_ADSP.

Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.

This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.

Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
2024-11-19 17:53:11 -05:00
Tomasz Leman
e0977dccd8 dts: xtensa: intel: Add hsbcap register node for ADSP ACE platforms
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.

In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-11-16 14:03:50 -05:00
Marek Matej
f3e70fdd75 dts: esp32s3: shm nodes update
Align the shared memories with the memory.h layout.
Reorder nodes to show memory related nodes together.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-11-08 11:36:09 -06:00
Gerard Marull-Paretas
f989711a60 pm: s/power-domain/power-domains and add power-domain-names
Some devices may belong to >1 power domain, so with the current design
this is something not possible to describe. It's worth to note that
Linux also uses the `power-domains` naming scheme, not `power-domain`.
This patch also introduces `power-domain-names` so that each entry in
`power-domains` can be given a name if needed. `#power-domain-cells`
is now required as well.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-10-18 17:45:21 +01:00
Laurentiu Mihalcea
cdd5635002 nxp: imx8m: adsp: enable the irqstr interrupt controller
Enable the irqstr interrupt controller for the adsp-based
imx8mp.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Tested-by: Daniel Baluta <daniel.baluta@nxp.com>
2024-10-18 14:16:21 +02:00
Laurentiu Mihalcea
1174ea522f dts: xtensa: nxp_imx8: add bus clock for sai1
Add bus clock for `sai1` node.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-10-17 10:48:38 -04:00
Laurentiu Mihalcea
fdbf4d23df dts: xtensa: nxp_imx8: add power domain for irqsteer
Add power domain DT node for the irqsteer and a reference to
it in irqsteer's DT node.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-10-11 09:27:57 +02:00
Iuliana Prodan
991eb0cd10 dts: xtensa: nxp: add mailbox node
Add mailbox node used for inter-process communication.
For DSP, we have a direct interrupt line to the core.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2024-10-02 13:40:20 -05:00
Daniel Leung
d0e2a62daf soc: xtensa: add sample_controller32
Add sample_controller32 for Xtensa which has MPU.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-10-02 09:58:36 +02:00
Grzegorz Bernat
a654bfbdfa soc: intel: renamed soc from ace30_ptl to ace30
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.

There is only one ptl platform, but there can be several ace30 platforms.

Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
2024-09-24 10:10:37 +02:00
Flavio Ceolin
0047d31eb9 intel_adsp: cavs20: Remove legacy files
Remove cavs20 leftover files.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-09-19 03:26:53 -04:00
Flavio Ceolin
72f2a04f7d intel_adsp: cavs18: Remove legacy files
Remove cavs18 leftover files.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-09-19 03:26:53 -04:00
Flavio Ceolin
b3acb149c5 intel_adsp: cavs15: Remove legacy files
cavs15 was removed long time ago, these are leftovers files that should
be removed as well.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-09-19 03:26:53 -04:00
Armin Kessler
576fc209c4 drivers: video: esp32s3: add support for cam interface
Adding support for the esp32s3 LCD_CAM peripheral.

Signed-off-by: Armin Kessler <ake@espros.com>
2024-09-06 11:26:59 -04:00
Flavio Ceolin
4902f189ae dts: xtensa: intel_adsp: Set soft-off state as disabled
The 'soft-off' state must be used when explicitly request by calling
`pm_state_force`. Set this state as disabled in dts ensures that the
pm policy manager will not use this state.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-09-02 11:54:08 +02:00
Sylvio Alves
f099bcd497 hotfix: drivers: i2s: update esp32s3/c3 I2S dtsi
I2S driver was merged after interrupt .dtsi was changed,
causing CI to fail. This updates it accordingly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-08-29 16:10:28 -04:00
Marcio Ribeiro
902104d795 drivers: i2s: esp32s3/esp32c3
i2s support added for esp32s3 and esp32c3

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-29 18:06:23 +02:00
Raffael Rostagno
dfbcb9dd60 dts: irq: esp32: Added priority and flags to device tree
Added IRQ priority and flags configuration to device tree.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-22 14:25:25 -04:00