Add support for PM. The strategy is as follows:
1) For level 1 interrupts: don't care, these don't
require the PM domain of irqsteer to be turned on
since they are, well, direct.
2) For level 2 interrupts: use the reference count
of the dispatchers.
Upon doing a get() on a dispatcher with its reference count
set to 0, before enabling the IRQ (meaning accessing the
reg. space) increment the reference count of the irqstr device
(which will result in the PM domain being enabled if 0).
Upon doin a put() on a dispatcher with its reference count
set to 1, after disabling the IRQ (meaning accessing the
reg. space) decrement the reference count of the irqstr device
(which will result in the PM domain being disabled if 0).
In summary, the PM domain of the device will be enabled if
at least one dispatcher is in use. On the other hand, the
PM domain of the device will be disabled if there's no
dispatchers in use (assuming there's no other dependencies).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, all dispatcher interrupts are enabled during
the driver init() function, which will cause a bus fault
unless the PM domain associated with irqsteer is powered on.
Since PM will be done during irq_enable()/irq_disable(),
add support for dynamically enabling/disabling dispatchers.
This way, the reg. space of the dispatchers will be accessed
when the PM domain is powered on.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, shared interrupts pose a big problem because
irq_disable() doesn't keep track of the number of clients
using that interrupt line. As such, add a reference count
mechanism which will stop the interrupt from being disabled
if there's still clients using it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Convert the compilation of the trigger type feature to depend
on Kconfig, following the same pattern of software-triggered
interrupt.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Implement `riscv_plic_irq_set_pending()` to trigger a
software-generated interrupt.
The "4. Interrupt Pending Bits" of the riscv-plic specs
described the reading of the pending bits, but not the writing
Since not all PLIC implementations support software-generated
interrupt, the function is compiled only when
`CONFIG_PLIC_SUPPORTS_SOFT_INTERRUPT` is enabled on PLIC that
supports it, such as the Andes' NCEPLIC100.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Correct several inconsistent parameter names in the following functions:
- stm32_gpio_intc_select_line_trigger: rename `trigger` to `trg`
to match the header file.
- stm32_gpio_intc_set_irq_callback: rename the callback argument to `user`
to match the `stm32_gpio_irq_cb_t` type.
- stm32_exti_get_line_src_port: rename `pin` to `line` to align with
the Doxygen comment and implementation.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The functions to obtain the address are hardcoded to return
the address of the first core when `CONFIG_SMP != y`, this
causes an issue with enabling an IRQ when there are more than
one core in the system (`CONFIG_MP_MAX_NUM_CPUS > 1`), as the
driver would first enable the IRQ on the first core, and when
it tries to obtain the address for the following cores and
disable the IRQ on them, the functions continue to return the
address of the first core, causing the IRQ to be disabled
on the first core.
Fix this by determine if `CONFIG_MP_MAX_NUM_CPUS > 1` instead
of `CONFIG_SMP=y` when returning the address.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
- Implement irq-set-affinity in RISCV PLIC.
- Added new affinity shell command to get/set the irq(s)
affinity in runtime, when `0` is sent as the `local_irq`, it
means set/get all IRQs affinity.
- Some minor optimizations
Updated the build_all test to build this new configuration.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Allow IRQs to work on every hart regardless of the mapping
of the contexts.
Add a test to validate the hart-context mapping.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Move the lock out from the `plic_irq_enable_set_state()` function
to cover the entire configuration process, so the whole of
enable/disable is atomic.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Adds a driver for the STM32WB0 series GPIO interrupt controller.
This driver implements the STM32 GPIO INTC API, along with an extension
function used to check if a specific line is available on current board.
This also extends the GPIO INTC API to support level-sensitive interrupts,
as this feature is available on STM32WB0.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
In corner case, the pending ISR will be triggered immediately
after enable the IRQ, this PR will setting CPU affinity first
to avoid routing the unexpected IRQ to other CPUs.
Signed-off-by: chao an <anchao@lixiang.com>
This commit rebrands the STM32 EXTI API to a more hardware-agnostic
"GPIO interrupt controller" API, in anticipation of the introduction of
new series lacking the EXTI peripheral. The GPIO and EXTI drivers are
updated to match the rebranded API.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit makes the contents of the stm32_exti_line_t data type opaque to
the EXTI GPIO interrupt controller API users. The GPIO driver is updated
to comply with this API change.
N.B.: while some assertions are removed as part of this commit, they were
broken since forever anyways, so nothing of value is lost.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Move the functions that interact with EXTI configuration registers to
select or get the GPIO port that triggers events on a given EXTI line
to the EXTI driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit reorders the functions in the EXTI driver.
Internal functions and exported functions are now grouped with each other.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit changes the EXTI driver API to use unsigned types
for all parameters previously typed as `int`, as the signedness
is unneeded and unwanted.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
All assertions performed in the EXTI drivers were wrong, as they passed
values to __ASSERT_NO_MSG instead of predicates. Update all assertions
to be actually useful.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using
CSR 'mnxti' and handles all pending interrupts before exiting the ISR.
When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode
and are claimed automatically. The RISC-V common ISR is used for interrupts
hooked into SW ISR table, but it only handle one pending interrupt per ISR.
This commit enhances CLIC to set vector mode for direct ISRs only and use
the CLIC common entry for regular ISRs to handles multiple pending
interrupts in an ISR.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Fixes repeated allocation of interrupt sources by successive calls
to esp_intr_alloc or esp_intr_enable for the same source.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Print the ISR & its ARG along with the IRQ and Hits in
`plic stats get <intc>` command, i.e.
```CONFIG_SYMTAB=n
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits ISR(ARG)
10 541 0x800054ee(0x80008170)
```
```CONFIG_SYMTAB=y
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits ISR(ARG)
10 114 uart_ns16550_isr(0x80008230)
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
In the it8xxx2 chip, the interrupt for INT0 is reserved. However,in some
stress tests, the unhandled IRQ0 issue occurs. To prevent the system from
going directly into kernel panic, we implemented a workaround by
registering interrupt number 0 and doing nothing in the IRQ0 handler.
The side effect of this solution is that when IRQ0 is triggered, it will
take some time to execute the routine. There is no need to worry about
missing interrupts because each IRQ's ISR is write-clear, and if the
status is not cleared, it will continue to trigger.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
add helper for interrupts, so multiple
instances of peripherals work.
this way out-off-tree peripherals are supported.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Both $ra and $t2 are caller-saved registers and may be modified in ISR
callback. Save $ra to stack to follow the calling convention.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
RISC-V trap entry is handled in soc/common/riscv-privileged/vector.S.
Remove the redundant modification in CLIC driver.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CLIC should be the first level interrupt controller because it replaces
the basic RISC-V local interrupt.
The interrupt level in CLIC controls preemption between IRQs, rather than
specifying the number of nested interrupt controllers.
Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Kconfig options in those drivers are visible and selectable
to any board/soc when it should not. This makes sure both
depends on proper family.
Fixes#74347
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Renesas RA ICU driver requires to generate ISR tables.
Adding `select GEN_ISR_TABLES` to force enable it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The documentation recommends to read and then write-back the entire
register, when ending interrupts.
Signed-off-by: Mateusz Karlic <mkarlic@antmicro.com>
Selection of these GIC Kconfigs have been deprecated
for more than 2 releases, users should use the devicetree
method instead, update the Kconfigs.
The SOCs below have been updated to not select `GIC_V3`, since
their devicetree already have the required compatible:
- fvp_aemv8r
- rzt2m
- rk3658
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Fix to properly allocate IRQs for interrupt sources over 60.
It also screens out non-allocatable IRQs used by the CPU.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Move it out of boot section because it's also called by none-boot function
'loapic_resume()' at runtime. Better to keep boot-only things in boot
section to avoid paging in boot section things at runtime.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add an interrupt controller driver for this device. This is an
extremely simple second level controller with per-interrupt-bit
registers for "enable" and "status". There is no internal latching,
so no "clear/ACK" process is needed.
Signed-off-by: Andy Ross <andyross@google.com>
Save the reference of the start index of the `_sw_isr_table`
to the config struct, so that the `local_irq` can be used as
offset directly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Previously the multi-level irq lookup table is generated by
looping through the devicetree nodes using macros & Kconfig,
which is hard to read and flimsy.
This PR shifts the heavy lifting to devicetree & DT macros such
that an interrupt controller driver, which has its info in the
devicetree, can register itself directly with the multi-level
interrupt architecture, which is more straightforward.
The previous auto-generated look up table with macros is now
moved in a file of its own. A new compatibility Kconfig:
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and
enabled by default to compile the legacy look up table for
interrupt controller drivers that aren't updated to support the
new architecture yet.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
VPR cores CLIC supports vectored mode only. Select
`GEN_IRQ_VECTOR_TABLE` such that it can't be disabled.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
DisableDeepSleepIRQ() disables the NVIC irq, while PINT need it to fire an
event when the interrupt is used. So while the interrupt is not used in
DeepSleep mode, it should still be available to be used.
Signed-off-by: Hessel van der Molen <hvandermolen@dexels.com>
arch_interface.h is for architecture and should not be
under sys/. So move it under include/zephyr/arch/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Process the GPIO_INT_WAKEUP flag and set appropraite bits
in the SoC to wakeup the system from deep sleep mode.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Clearing virtual wire interrupt after calling callback may cause
interrupt miss if the same virtual wire changes due to action
in handler.
e.g. HOST_RST_WRN pulse within 50 us
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Updated the shared IRQ handler function in the shared interrupt controller
drivers to include support for the 'irq_number' parameter. When a single
driver manages multiple shared IRQs, it becomes challenging to determine
which IRQ line is invoking the handler. Therefore, I've introduced an
option to share the IRQ number to address this issue.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
According to the clic specification
(https://github.com/riscv/riscv-fast-interrupt), the mnxti register has
be written, in order to clear the pending bit for non-vectored
interrupts. For vectored interrupts, this is automatically done.
From the spec:
"If the pending interrupt is edge-triggered, hardware will automatically
clear the corresponding pending bit when the CSR instruction that
accesses xnxti includes a write."
I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom
irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented.
For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that
handles the pending interrupts according to the pseudo code in the spec.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
The mechanism for hardware vectoring has changed in the clic spec
(https://github.com/riscv/riscv-fast-interrupt) in 2019. Before
vectoring was enabled via `mode` bits in `mtvec`. Support for this was
added in fc480c9382.
With more current clic implementations, this does not work anymore.
Changing the `mode` bits is reserved. Vectoring can be enabled
individually in the `shv` bit of `clicintattr[i]`.
Since the old mechanism is still used, I added a new Kconfig for it.
If this Kconfig is not set, we use the `shv` bit for harware vectoring.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
The trig field of clicintattr is indeed in bits 2:1. However, the mask
`CLIC_INTATTR_TRIG_Msk` is only applied directly to the bitfield
`INTATTR.b.trg`. Therefore it doesn't have to be shifted additionally.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
Interrupt trigger type register each bit indicate the configured interrupt
type. bit value is 0 indicate level trigger interrupt, 1 indicate edge
trigger interrupt.
The level trigger defined to ~BIT(0) equal 0xfffffffe not equal 0.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Store the compile-time computed length of the `irq_count` into
a variable so that we have less to do in runtime.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Change the index variable type to `int` from `size_t` to compile
across 32bit and 64bit platforms without generating warnings.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Don't execute `irq_enable` in process of the `ra_icu_irq_connect_dynamic`.
The caller of `ra_icu_irq_connect_dynamic` is only `gpio_ra_pin_configure`
at this time. `gpio_ra_pin_configure` calls `irq_enable` just after called
`ra_icu_irq_connect_dynamic`.
So removing 'irq_enable' from 'ra_icu_irq_connect_dynamic' has no effect
on behavior.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Information about IOAPIC can be located not in the first
DMAR Hardware Unit Definition subtable. Iterate them all.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The plic has a very simple mechanism to claim an interrupt as well as to
complete and clear it. The same register is read from/ written to to
achieve this.
Get the ID of the HART that serviced the interrupt and write to the
claim complete register in the correct context
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
The plic uses contexts to seperate irq enables, threshold priority and
claim complete registers from each core for a given platform. As well as
this, each privilege level has its own context.
for multi-core platform's, we need to be able to enable/ disable a
global interrupt for all the cores that are associated with Zephyr.
To do this, we need to make some assumptions:
1. The privilege contexts are contiguous
2. M mode context is first, followed by S mode.
We know how many cpus are used in an application and each cpu's hartid,
thanks to some very handy inline functions. So we iterate through each
cpu and use the hartid of a cpu in the calculation of the context.
While we are at it, In an effort to make the driver more readable,
allign with the macro naming convention outlined in Linux's PLIC driver
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Multilevel interrupt configs are leaking into every single build without
this option being enabled, so guard the Kconfig and include files to
avoid this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define the edge-trigger register base address based on whether
the PLIC node in the devicetree has an additional compatible
that supports edge-triggered interrupt.
Limited the implementation to Andes NCEPLIC100 only, updated
the devicetree binding of `andes_v5_ae350` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit introduces a new interrupt controller driver used
for NXP's IRQ_STEER IP.
Apart from introducing the driver itself, this commit contains
the following changes:
1) Switch i.MX8MP to using the XTENSA core interrupt
controller instead of the dummy irqsteer one.
* this is required because the binding for the
irqsteer driver is no longer a dummy one
(since it's being used by the irqsteer driver).
As such, to avoid having problems, switch to
using another dummy binding.
2) Modify the irqsteer dummy binding such that it
serves the IRQ_STEER driver's needs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
There's a ternary operator that depends on configuration-defined macro:
`CONFIG_DYNAMIC_INTERRUPTS` is not enabled by default
for any of the platforms that use PLIC,
it is possbile to set it to `=y` though.
This triggered the Coverity check to report it as dead code.
Fixes#65576.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
The `riscv_plic_irq_enable` & `riscv_plic_irq_disable` are very
similar, refactor them out into `plic_irq_enable_set_state`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Introduced `CONFIG_PLIC_SHELL` to enable the build of shell
debugging command to get the hit count of each interrupt
controller's IRQ line. This is especially useful when working
with dynamically installed ISRs, which will be the case for
`plic_sw`.
Example usage:
```
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 177
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 236
uart:~$ plic stats clear interrupt-controller@c000000
Cleared stats of interrupt-controller@c000000.
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits
==================
10 90
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Maxim Adelman <imax@meta.com>
if-conditionals should have brackets according to Zephyr's
coding standard, and explicitly compares `edge_irq` against 0.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Previously, the PLIC's registers were accessed through uint32_t *,
so all calculated offsets were effectively multiplied by
sizeof(uint32_t). Do the same manuallly now that we have
mem_addr_t/sys_read32.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
`get_claim_complete_offset` and `get_threshold_priority_offset` actually
return addresses directly. Rename them to `_addr` for consistency within
the driver. Also change their return type to `mem_addr_t`.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations
fixes#62956
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.
Converted manual bit shift/set/unset to use macros provided by
Zephyr.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.
The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
