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riscv: irq: Correct CLIC_INTATTR_TRIG_Msk

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The trig field of clicintattr is indeed in bits 2:1. However, the mask
`CLIC_INTATTR_TRIG_Msk` is only applied directly to the bitfield
`INTATTR.b.trg`. Therefore it doesn't have to be shifted additionally.

Signed-off-by: Greter Raffael <rgreter@baumer.com>
This commit is contained in:
Greter Raffael 2023-12-21 12:41:59 +00:00 committed by Carles Cufí
parent 1217656a24
commit bc2e157cba
1 changed files with 1 additions and 3 deletions
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4
drivers/interrupt_controller/intc_nuclei_eclic.c
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@ -88,10 +88,8 @@ struct CLICCTRL {
/** ECLIC Mode mask for MTVT CSR Register */
#define ECLIC_MODE_MTVEC_Msk 3U
/** CLIC INTATTR: TRIG Position */
#define CLIC_INTATTR_TRIG_Pos 1U
/** CLIC INTATTR: TRIG Mask */
#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos)
#define CLIC_INTATTR_TRIG_Msk 0x3U
#define ECLIC_CFG (*((volatile union CLICCFG *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 0))))
#define ECLIC_INFO (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1))))