Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
Avoid entering low-power state during I2C host transfers in PIO mode.
Entering a low-power state during an active PIO transfer may prevent
the peripheral from generating the clock signal correctly,
resulting in transmission errors.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Avoid entering low-power state during I2C host transfers in PIO mode.
Entering a low-power state during an active PIO transfer may prevent
the peripheral from generating the clock signal correctly,
resulting in transmission errors.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Avoid entering low-power state during I2C host transfers in PIO mode.
Entering a low-power state during an active PIO transfer may prevent
the peripheral from generating the clock signal correctly,
resulting in transmission errors.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move handling of write-to-clear status and stop detect to the
beginning of the ISR for PIO mode to reduce unnecessary clock
stretching and improve responsiveness during transfers.
This patch also separates status clearing for shared FIFO mode,
ensuring it is done at the appropriate point after data handling
completes, maintaining correct transfer behavior.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Previously, the clock_frequency property defined in the Device Tree was
not applied to the I2C controller, causing the controller to ignore the
specified bitrate configuration if no other config for speed. When using
default hardware settings, the lack of an explicit timing or frequency
config may result in the controller ignoring bitrate settings. This change
ensures that the clock_frequency value from DTS is now correctly mapped
and set during controller initialization, allowing the bitrate to take
effect as intended. This improves hardware configurability and ensures
the I2C bus operates at the desired speed specified in the Device Tree.
Signed-off-by: Xiaolu Sun <xiaolu.sun@intel.com>
This commit adds support for configuring two user-defined target
addresses in the I2C target driver.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Driver simply registered itself without setting the level based on the
I2C Kconfig which wasn't quite right, need the log level set based on
the Kconfig for I2C.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The STM32F7 family does not yet support power management in Zephyr.
Besides, LL_I2C_EnableWakeUpFromStop and LL_I2C_DisableWakeUpFromStop
are not implemented in the H7 HAL/LL drivers
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Drop LOG_ERR calls from driver level related to transfer calls.
Application can handle the result and decide whether to log or not.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fix I2C target implementation so NACKs are issued if the callback returns
an error. This allows for proper signaling to the I2C host when commands
or data are invalid for the I2C target.
Signed-off-by: Alex Hogen <alex@edt.com>
Fix compile error due to unknown macro when building CONFIG_I2C_TARGET for
Silabs Thunderboard EFM32GG12 (SLTB009A). The previous macro exists in
(all?) EFR32 part headers but not EFM32.
Signed-off-by: Alex Hogen <alex@edt.com>
The extra shell commands are useless unless you also enable
I2C_TARGET. Conditionally include them based on the I2C_TARGET
kconfig.
Signed-off-by: Yuval Peress <peress@google.com>
The original definition of request_bytes as uint8_t caused incorrect
behavior when attempting to receive more than 256 bytes, as the variable
would overflow. This patch changes its type to uint32_t to allow
correct tracking of large I2C transfers.
Signed-off-by: Eason Huang <eason.huang@tronfuture.com>
The issue is found when doing shell command "i2c scan" on sama7g54-ek.
In this case no data will be transferred besides START and STOP. Data
abort would occur on accessing "msg->buf[msg->idx++]" when MMU is
enabled and "msg->idx" is very large.
Signed-off-by: Tony Han <tony.han@microchip.com>
Drop few CONFIG_PM_DEVICE_RUNTIME guards, the pm_device_runtime
functions they are masking are no-op automatically when the
corresponding config option is not selected.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Current code only calls pm_device_runtime_get when registering target
devices if the device is marked as wakeup capable by the application.
This does quite work for a setup with PM=n and PM_DEVICE=y and
PM_DEVICE_RUNTIME=y, where the CPU does not really go in stop mode ever,
and results in the i2c target device not working at all.
Fix this by always claiming the device when PM_DEVICE_RUNTIME is
enabled.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add initial support for i2c on Renesas RX MCU
This driver is controlling the RIIC HW of RX MCU for i2c bus
interface on Zephyr
Only master mode is supported
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Implement I2C target mode in STM32 I2C RTIO drivers. The implementation
in respectively i2c_ll_stm32_v1_rtio.c and i2c_ll_stm32_v2_rtio.c is
based on the implementation of the non-RTIO drivers, respectively
i2c_ll_stm32_v1.c and i2c_ll_stm32_v2_rtio.c.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct management of I2C write transfers that are driven from 2
I2C messages, one for the transfer of the address to write
to and a following message for the transfer of the data to be written.
In this case, no START and STOP bit should be triggered between the 2
I2C transfers.
In STM32 I2C v1 driver, this simply means not emitting a START
condition when the input sequence does not set the RESTART flag.
In STM32 I2C v2 driver, this can only be achieved using the SoC I2C
controller Reload Mode feature, hence update Reload Mode implementation
to use reload mode for both transfers over 255 bytes (splitted in
chunks) and for cases where no STOP and START bits are emitted between
2 transfer in the same transaction.
Regarding STM32 I2C v2 driver, the reload mode must be enable before the
first transaction, known that it's needed due to the following
transaction. Therefore we need to parse the messages grouped in the same
transaction to detect such sequences (a message without STOP flag
followed by a message without RESTART flag) and when so, pass the
information to the I2C driver through RTIO framework. To achieve that,
let's use a free bit from I2C message flags (bit 7) in the message
for which we need to enable SoC ReloadMode from the first transfer.
We check that this bit flag is not used by the I2C framework prior
using it.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The first transfer in an I2C transaction series must always set
the RESTART flag. Since this is not always done by callers,
enforce the flag is set, both in the I2C API and RTIO API entry
points of STM32 I2C RTIO drivers.
Add a sanity test in STM32 I2C v2 RTIO driver on transaction
chunks regarding RESTART and STOP flags, as done on the non-RTIO
driver.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit prevents the hardware from generating an unexpected
target slave address match ISR by the following change:
1. Enable the New Match Interrupt Enable bit (NMINTEN) only when
necessary.
2. Explicitly clear all SMBnADDRx registers because they are not
cleared when the I2C hardware is disabled. It will cause the
asynchrinization between SMBnADDRx and registered_target_mask if the
system jumps from the RO image to the RW image.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
For testing/debugging purposes, it will be possible then to register
or unregister an i2c target.
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
When using target mode, we've found that some times the msg field can
be null through some of the code paths of the interrupt event handler.
Signed-off-by: Yuval Peress <peress@google.com>
Some macros haven't been properly renamed in previous commits.
Fixes the wrong names that caused compilation errors.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Only include cmsis_core.h on ARM platforms, including it unconditionally
as it is now causes a build failure on all other platforms, namely x86
on the weekly build run.
Tested with:
west build -p -b up_squared/apollo_lake tests/drivers/build_all/led
(and others)
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Follow-up to PR #88631: fix missing variable declarations introduced in
the STM32 I2C LL driver after adding timeouts to blocking loops.
The missing declarations caused a build failure when interrupts were
disabled (CONFIG_I2C_STM32_INTERRUPT=n).
Fixes a regression introduced in #88631.
Signed-off-by: Jean Nanchen <jean.nanchen@gmail.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
'timings' is an array of 'struct i2c_config_timing' (3 x uint32_t).
'i2c_timings_##index' is an array of uint32_t (hence the cast when it
is assigned to 'timings'). Therefore 'ARRAY_SIZE(i2c_timings_##index)' is
off by a factor 3 when used for n_timings.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Fix npcx_i2c_ctrl_transfer arguments to match header to prevent
warning: type of 'npcx_i2c_ctrl_transfer' does not match original
declaration
Signed-off-by: Al Semjonovs <asemjonovs@google.com>
Remove redundant ifdef exclusion of calls to
pm_policy_device_power_lock_get() and
pm_policy_device_power_lock_put().
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Since the __IO macro use has been removed, make the whole reg pointer
volatile. This is similar to what is done in the gpio-davinci driver.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Some I2C peripherals like TI charger or gauge chips need support for I2C
clock stretching. This patch includes that and makes these modules
usable with I2C emulation over GPIO.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
base on DesignWare I2C driver to implement RTS5912 I2C driver.
1. support customize bus recovery function.
2. fix isr timing issue by enable tx empty control.
3. support stuck at low handle by enable bus clear feature.
4. support custom stuck at low timeout set from dts
5. disable block mode in rts5912 i2c.
6. support I2C_ALLOW_NO_STOP_TRANSACTIONS
Signed-off-by: Titan Chen <titan.chen@realtek.com>
The current I2C driver assumes that at least one byte will be read in CQ
(command queue) mode. However, when a 0-byte read is issued
(e.g., by cmd_i2c_scan),
The read handler uses (len - 1) to set the command queue length.
When len is 0, this underflows to 0xFF, leading to an incorrect transfer
length and possible crash.
To fix this, add a check in cq_mode_allowed() for reads with length 0:
-Fallback to PIO mode in such cases.
-Properly handle 0-byte reads by issuing STOP (E_FINISH) when the slave
address is acknowledged.
-Add appropriate handling for NACK conditions when the slave address is
not acknowledged.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
