zephyr/dts/riscv
Miguel Gazquez be9549be60 soc: Add support for the WCH CH32V303
Adds support for building an image for the ch32v303.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-05-24 18:03:53 +02:00
..
aesc dts: riscv: Add aesc 2025-05-14 14:09:41 +02:00
andes
bflb dts: bflb: Enable efuse driver on bl60x 2025-05-19 10:11:58 +02:00
efinix
espressif soc: esp32c6: i2s: Add support 2025-05-22 15:25:12 +02:00
gd driver: interrupt_controller: intc_clic: rework to standard CLIC driver 2025-04-04 14:55:50 +02:00
ite drivers: crypto: add it51xxx sha256 driver 2025-05-16 19:07:37 +02:00
lowrisc
microchip
niosv
nordic dts: nordic: nrf54: Add nRF54L09 FLPR 2025-03-28 08:34:23 +01:00
openhwgroup soc: cva6: Add device tree node for RISC-V mtimer 2025-04-18 17:46:30 +02:00
openisa
qemu
sensry dts: sy1xx: add support for i2c 2025-03-14 14:39:55 +01:00
sifive
starfive
telink
wch soc: Add support for the WCH CH32V303 2025-05-24 18:03:53 +02:00
neorv32.dtsi dts: bindings: gpio: neorv32: require interrupt property to be set 2025-05-06 13:01:20 +02:00
renode_riscv32_virt.dtsi
riscv32-litex-vexriscv.dtsi boards: litex: vexriscv: add litei2c controller 2025-03-27 14:01:11 +01:00