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soc: cva6: Add device tree node for RISC-V mtimer

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The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit is contained in:
Eric Ackermann 2025-04-11 18:11:24 +02:00 committed by Benjamin Cabé
parent 590258b381
commit e367e1d607
3 changed files with 17 additions and 1 deletions
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4
boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.dts
View File

@ -30,6 +30,10 @@
status = "okay";
};
&mtimer {
status = "okay";
};
&eth {
local-mac-address = [00 18 3e 02 e3 7f];
status = "okay";

6
boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.dts
View File

@ -26,7 +26,11 @@
status = "okay";
};
&clint{
&clint {
status = "okay";
};
&mtimer {
status = "okay";
};

8
dts/riscv/openhwgroup/cva6.dtsi
View File

@ -93,6 +93,14 @@
status = "disabled";
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
status = "disabled";
};
/*
* Xilinx AXI DMA.
* Part of the Xilinx AXI Ethernet Subsystem.