Eric Ackermann 39babba9a9 soc: add OpenHW Group CVA6 SoC ... Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>		2025-04-11 13:33:50 +02:00
..
altr,nios2f.yaml
andes,andescore-v5.yaml
arm,cortex-a53.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
arm,cortex-a55.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
arm,cortex-a72.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
arm,cortex-a76.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
arm,cortex-m0.yaml
arm,cortex-m0+.yaml
arm,cortex-m1.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m33f.yaml
arm,cortex-m55.yaml
arm,cortex-m55f.yaml
arm,cortex-m85.yaml
arm,cortex-m85f.yaml
arm,cortex-m.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
arm,cortex-r7.yaml
arm,cortex-r52.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
arm,cortex-r82.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
cdns,tensilica-xtensa-lx3.yaml
cdns,tensilica-xtensa-lx4.yaml
cdns,tensilica-xtensa-lx6.yaml
cdns,tensilica-xtensa-lx7.yaml
cpu.yaml
efinix,vexriscv-sapphire.yaml
espressif,riscv.yaml
espressif,xtensa-lx6.yaml	dts: espressif: Streamline device tree binding descriptions	2025-03-04 18:26:43 +00:00
espressif,xtensa-lx7.yaml	dts: espressif: Streamline device tree binding descriptions	2025-03-04 18:26:43 +00:00
gaisler,leon3.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
intel,alder-lake.yaml
intel,apollo-lake.yaml
intel,bartlett-lake.yaml	boards: intel: btl: Adds Bartlett Lake board	2025-03-29 07:44:22 -04:00
intel,elkhart-lake.yaml
intel,ish.yaml
intel,lakemont.yaml
intel,niosv.yaml
intel,raptor-lake.yaml
intel,x86.yaml
ite,riscv-ite.yaml
litex,vexriscv-standard.yaml
lowrisc,ibex.yaml
neorv32,cpu.yaml	dts: bindings: neorv32: use vendor prefix	2025-03-11 05:36:35 +01:00
nordic,vpr.yaml
nuclei,bumblebee.yaml
openhwgroup,cva6.yaml	soc: add OpenHW Group CVA6 SoC	2025-04-11 13:33:50 +02:00
openisa,ri5cy.yaml
openisa,zero-ri5cy.yaml
qemu,nios2-zephyr.yaml
qemu,riscv-virt.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
riscv,cpus.yaml
sample_controller.yaml
sensry,ganymed-sy1xx.yaml	soc: sensry: Add support for SY120-GBM and SY120-GEN1	2024-09-16 20:19:31 +02:00
sifive-common.yaml
sifive,e24.yaml
sifive,e31.yaml
sifive,e51.yaml
sifive,s7.yaml
sifive,u54.yaml
snps,arcem.yaml
telink,b91.yaml
wch,qingke-v2.yaml	dts: riscv: include riscv,cpus.yaml in qingke-v2	2025-01-15 11:58:58 +01:00
wch,qingke-v4c.yaml	soc: Introduce Qingke V4C-based CH32V208 SoC	2025-03-14 14:39:30 +01:00
zephyr,native-posix-cpu.yaml	dts: cpu: Make descriptions consistent	2025-02-25 07:55:09 +01:00
zephyr,native-sim-cpu.yaml	dts: zephyr,native-posix-cpu changed to zephyr,native-sim-cpu	2025-03-12 02:27:36 +01:00