Flavio Ceolin f3bec2ffee xtensa: tls: Fix invalid reference ... bsa is not defined. It should be access through frame pointer. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>		2023-05-11 17:38:16 -04:00
..
include	arch: xtensa: core: include: Update header to use guard macros	2022-07-20 13:39:23 -05:00
offsets	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
startup
CMakeLists.txt
coredump.c	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
cpu_idle.c
crt1.S
debug_helpers_asm.S	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
fatal.c	xtensa: limit speical exit() to XT_SIMULATOR	2023-05-08 09:59:54 +02:00
gdbstub.c	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
gen_zsr.py
irq_manage.c
irq_offload.c	include: add missing zephyr/irq.h include	2022-10-17 22:57:39 +09:00
README-WINDOWS.rst
timing.c	includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>	2022-09-05 16:31:47 +02:00
tls.c
window_vectors.S
xcc_stubs.c
xtensa_backtrace.c	xtensa: use lower-case hex in backtrace output	2022-09-09 14:09:33 -05:00
xtensa_intgen.py
xtensa_intgen.tmpl
xtensa-asm2-util.S	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
xtensa-asm2.c	xtensa: tls: Fix invalid reference	2023-05-11 17:38:16 -04:00