zephyr/soc/nxp/s32
Dat Nguyen Duy e4539aa9c9 board: s32z2xxdc2: allow the code to be executed from code RAM
- Trace32 runner: no need to configure TE bit in CFG_CORE
register in the cmm start-up script, it can be configured
at Zephyr start-up code when required (via SCTRL register)

- MPU static regions also needs to be updated for XIP and
non-XIP

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2024-11-26 15:43:45 -05:00
..
common soc: nxp: s32: convert power mng to native drivers 2024-08-02 21:51:12 -05:00
s32k1 soc: nxp: consolidate nxp port pinctrl headers 2024-11-22 13:01:02 -06:00
s32k3 soc: nxp: s32k: make the SoCs SEGGER RTT capable 2024-11-18 07:25:40 -05:00
s32ze board: s32z2xxdc2: allow the code to be executed from code RAM 2024-11-26 15:43:45 -05:00
CMakeLists.txt
Kconfig soc: nxp: s32: convert power mng to native drivers 2024-08-02 21:51:12 -05:00
Kconfig.defconfig
Kconfig.soc
soc.yml