Dat Nguyen Duy e4539aa9c9 board: s32z2xxdc2: allow the code to be executed from code RAM ... - Trace32 runner: no need to configure TE bit in CFG_CORE register in the cmm start-up script, it can be configured at Zephyr start-up code when required (via SCTRL register) - MPU static regions also needs to be updated for XIP and non-XIP Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>		2024-11-26 15:43:45 -05:00
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common	soc: imxrt: Fix flexspi xip configuration issue	2024-09-10 14:42:15 +01:00
imx	soc: nxp: imx95: A55: enable SDK cache driver	2024-11-25 12:16:33 +01:00
imxrt	soc: nxp: imxrt: imxrt118x: add flexspi support	2024-11-20 16:00:02 -05:00
kinetis	soc: nxp: consolidate nxp port pinctrl headers	2024-11-22 13:01:02 -06:00
layerscape	soc: Remove re-defining some defined types	2024-11-18 07:41:23 -05:00
lpc	soc: arm: nxp: lpc55xx flexcomm 3->7 clock init	2024-11-16 14:06:54 -05:00
mcx	soc: nxp: consolidate nxp port pinctrl headers	2024-11-22 13:01:02 -06:00
rw	soc: nxp: rw: Introduce HAS_NXP_MONOLITHIC_BT config	2024-10-18 17:45:07 +01:00
s32	board: s32z2xxdc2: allow the code to be executed from code RAM	2024-11-26 15:43:45 -05:00