e0977dccd8
This commit introduces the L2 Memory Capabilities (hsbcap) register node to the Devicetree specifications for Intel ADSP ACE platforms. The hsbcap register provides information on the general capabilities associated with the L2 memory, which is critical for system configuration and resource management. The hsbcap node has been added to the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE 3.0 (PTL) platforms. In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to use the Devicetree node label for hsbcap, ensuring a consistent and maintainable approach to accessing this register across the codebase. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
180 lines
5.9 KiB
C
180 lines
5.9 KiB
C
/*
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* Copyright (c) 2024 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/toolchain.h>
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#include <adsp-vectors.h>
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#include <mem_window.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define L2_VIRTUAL_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0virtual)))
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#define L2_VIRTUAL_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0virtual)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* L3 region (IMR), located in host memory */
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#define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1)))
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#define L3_MEM_SIZE (DT_REG_SIZE(DT_NODELABEL(imr1)))
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#define L3_MEM_PAGE_SIZE (DT_PROP(DT_NODELABEL(imr1), block_size))
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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/* FIXME: most of these macros aren't related to the bootloader */
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#define IMR_BOOT_LDR_MANIFEST_OFFSET 0x42000
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#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
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#define IMR_BOOT_LDR_MANIFEST_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_MANIFEST_OFFSET)
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#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x180
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + IMR_BOOT_LDR_MANIFEST_SIZE)
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#define IMR_BOOT_LDR_LIT_SIZE 0x40
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#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
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IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
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#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
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#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
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#define IMR_BOOT_LDR_DATA_OFFSET 0x49000
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#define IMR_BOOT_LDR_DATA_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_DATA_OFFSET)
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#define IMR_BOOT_LDR_DATA_SIZE 0xA8000
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#define IMR_BOOT_LDR_BSS_OFFSET 0x110000
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#define IMR_BOOT_LDR_BSS_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_BSS_OFFSET)
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#define IMR_BOOT_LDR_BSS_SIZE 0x40000
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/* stack to be used at boot, when RAM is not yet powered up */
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#define IMR_BOOT_LDR_STACK_BASE (IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE)
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#define IMR_BOOT_LDR_STACK_SIZE 0x1000
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/* position of L3 heap, size of L3 heap - till end of the L3 memory */
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/* !!! FIXME: L3 heap base MUST be automatically calculated. !!! */
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#define IMR_L3_HEAP_BASE (IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE)
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#define IMR_L3_HEAP_SIZE (L3_MEM_SIZE - \
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(IMR_L3_HEAP_BASE - L3_MEM_BASE_ADDR))
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
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/* L1 init */
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#define ADSP_L1CC_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccap)))
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#define ADSP_CxL1CCAP_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccap)))
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#define ADSP_CxL1CCFG_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccfg)))
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#define ADSP_CxL1PCFG_ADDR (DT_REG_ADDR(DT_NODELABEL(l1pcfg)))
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#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
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#define ADSP_CxL1CCAP_REG (*(volatile uint32_t *)(ADSP_CxL1CCAP_ADDR))
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#define ADSP_CxL1CCFG_REG (*(volatile uint32_t *)(ADSP_CxL1CCFG_ADDR))
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#define ADSP_CxL1PCFG_REG (*(volatile uint32_t *)(ADSP_CxL1PCFG_ADDR))
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#endif /* (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)) */
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/* The number of set associative cache way supported on L1 Data Cache */
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#define ADSP_CxL1CCAP_DCMWC ((ADSP_CxL1CCAP_REG >> 16) & 7)
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/* The number of set associative cache way supported on L1 Instruction Cache */
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#define ADSP_CxL1CCAP_ICMWC ((ADSP_CxL1CCAP_REG >> 20) & 7)
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#ifndef _LINKER
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/* L2 Local Memory Management */
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/* These registers are for the L2 memory control and status. */
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#define DFL2MM_REG (DT_REG_ADDR(DT_NODELABEL(hsbcap)))
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struct ace_l2mm {
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uint32_t l2mcap;
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uint32_t l2mpat;
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uint32_t l2mecap;
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uint32_t l2mecs;
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uint32_t l2hsbpmptr;
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uint32_t l2usbpmptr;
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uint32_t l2usbmrpptr;
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uint32_t l2ucmrpptr;
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uint32_t l2ucmrpdptr;
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};
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#define ACE_L2MM ((volatile struct ace_l2mm *)DFL2MM_REG)
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/* DfL2MCAP */
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struct ace_l2mcap {
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uint32_t l2hss : 8;
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uint32_t l2uss : 4;
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uint32_t l2hsbs : 4;
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uint32_t l2hs2s : 8;
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uint32_t l2usbs : 5;
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uint32_t l2se : 1;
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uint32_t el2se : 1;
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uint32_t rsvd32 : 1;
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};
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#define ACE_L2MCAP ((volatile struct ace_l2mcap *)DFL2MM_REG)
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static ALWAYS_INLINE uint32_t ace_hpsram_get_bank_count(void)
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{
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return ACE_L2MCAP->l2hss;
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}
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static ALWAYS_INLINE uint32_t ace_lpsram_get_bank_count(void)
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{
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return ACE_L2MCAP->l2uss;
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}
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struct ace_hpsram_regs {
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/** @brief power gating control */
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uint8_t HSxPGCTL;
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/** @brief retention mode control */
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uint8_t HSxRMCTL;
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uint8_t reserved[2];
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/** @brief power gating status */
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uint8_t HSxPGISTS;
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uint8_t reserved1[3];
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};
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struct ace_lpsram_regs {
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/** @brief power gating control */
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uint8_t USxPGCTL;
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/** @brief retention mode control */
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uint8_t USxRMCTL;
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uint8_t reserved[2];
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/** @brief power gating status */
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uint8_t USxPGISTS;
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uint8_t reserved1[3];
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};
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#endif
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/* These registers are for the L2 HP SRAM bank power management control and status.*/
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#define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm)))
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#define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm)))
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#define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \
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(L2_HSBPM_BASE + L2_HSBPM_SIZE * (block_idx)))
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/* These registers are for the L2 LP SRAM bank power management control and status.*/
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#define L2_LSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(lsbpm)))
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#define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm)))
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#define LPSRAM_REGS(block_idx) ((volatile struct ace_lpsram_regs *const) \
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(L2_LSBPM_BASE + L2_LSBPM_SIZE * (block_idx)))
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#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
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