zephyr/soc/intel/intel_adsp/ace
Daniel Leung 22de29e768 soc: intel_adsp/ace: put syscall helpers in vector code section
This puts the syscall helpers into the vector code section, and
is a tiny TLB optimization. Before this, worst case scenario is
that there would 2 instruction TLB misses when both the syscall
helpers and the vector code pages are not in TLB cache. With
this change, there would be at most 1 instruction TLB miss as
now the syscall helper and the vector code (which includes
exception handling code and xtensa_do_syscall()) are now in
the same page, and the same TLB entry.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-11-26 00:12:18 +01:00
..
include dts: xtensa: intel: Add hsbcap register node for ADSP ACE platforms 2024-11-16 14:03:50 -05:00
_soc_inthandlers.h
ace-link.ld soc: intel_adsp/ace: put syscall helpers in vector code section 2024-11-26 00:12:18 +01:00
asm_memory_management.h soc: intel_adsp: ace: Use DT macros instead of hardcoded values 2024-11-16 14:03:50 -05:00
boot.c
CMakeLists.txt soc: intel: renamed soc from ace30_ptl to ace30 2024-09-24 10:10:37 +02:00
comm_widget_messages.c
comm_widget.c
comm_widget.h style: soc: comply with MISRA C:2012 Rule 15.6 2024-09-11 07:40:35 -04:00
irq.c
Kconfig Revert parts of "soc: intel: move init code from SYS_INIT to hooks" 2024-09-23 18:13:17 -04:00
Kconfig.defconfig.ace15_mtpm
Kconfig.defconfig.ace20_lnl
Kconfig.defconfig.ace30 soc: intel: renamed soc from ace30_ptl to ace30 2024-09-24 10:10:37 +02:00
Kconfig.defconfig.series
Kconfig.soc soc: intel: renamed soc from ace30_ptl to ace30 2024-09-24 10:10:37 +02:00
linker.ld
mmu_ace30.c soc: intel_adsp/ace30: do not map 0x0 2024-11-25 08:30:57 +01:00
multiprocessing.c Revert parts of "soc: intel: move init code from SYS_INIT to hooks" 2024-09-23 18:13:17 -04:00
pmc_interface.h
power_down.S soc: intel_adsp: ace: Update power_down to use new HPSRAM power-down macro 2024-11-16 14:03:50 -05:00
power.c soc: intel_adsp: ace: Update power_down to use new HPSRAM power-down macro 2024-11-16 14:03:50 -05:00
sram.c soc: intel_adsp: ace: Configurable SRAM retention mode and cleanup 2024-09-05 16:56:56 -04:00
timestamp.c