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zephyr/arch/x86
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Tomasz Bursztyka 5e4e0298e9 arch/x86: Generalize cache manipulation functions 
We assume that all x86 CPUs do have clflush instructions.
And the cache line size is now provided through DTS.

So detecting clflush instruction as well as the cache line size is no
longer required at runtime and thus removed.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-02-15 09:43:30 -05:00
..
core arch/x86: Generalize cache manipulation functions 2021-02-15 09:43:30 -05:00
include x86: rename CONFIG_SSE* to CONFIG_X86_SSE* 2021-02-15 08:21:15 -05:00
zefi license: add missing SPDX headers 2021-02-11 08:05:16 -05:00
CMakeLists.txt timing: add support for x86 2020-09-05 13:28:38 -05:00
gen_gdt.py x86: add support for thread local storage 2020-10-24 10:52:00 -07:00
gen_idt.py x86: gen_idt.py: typo fix 2020-05-21 14:44:33 +02:00
gen_mmu.py toolchain: add GEN_ABSOLUTE_SYM_KCONFIG() 2021-02-02 09:23:45 -05:00
ia32.cmake x86: add kconfigs and compiler flags for MMX and SSE* 2021-02-15 08:21:15 -05:00
intel64.cmake x86: add kconfigs and compiler flags for MMX and SSE* 2021-02-15 08:21:15 -05:00
Kconfig x86: add kconfigs and compiler flags for MMX and SSE* 2021-02-15 08:21:15 -05:00
timing.c x86: use TSC for timing information 2021-01-22 11:05:30 -05:00