Tomasz Bursztyka 5e4e0298e9 arch/x86: Generalize cache manipulation functions ... We assume that all x86 CPUs do have clflush instructions. And the cache line size is now provided through DTS. So detecting clflush instruction as well as the cache line size is no longer required at runtime and thus removed. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>		2021-02-15 09:43:30 -05:00
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arc	linker: remove asterisk from IRQ/ISR section name macro	2021-01-26 16:24:11 -05:00
arm	aarch64: mmu: Remove SRAM memory region	2021-02-15 08:07:55 -05:00
common	gen_isr_tables: Added check of the IRQ num before accessing the vt	2021-01-24 10:12:54 -05:00
nios2	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	arch/riscv: boost default stacks	2021-01-15 13:06:33 -05:00
sparc	lib/os/heap: introduce option to force big heap mode	2021-01-24 10:11:11 -05:00
x86	arch/x86: Generalize cache manipulation functions	2021-02-15 09:43:30 -05:00
xtensa	soc/intel_adsp: Move KERNEL_COHERENCE to cavs15	2021-02-11 14:47:40 -05:00
CMakeLists.txt	cmake: fix include directories to work with out-of-tree arch	2020-08-05 08:06:07 -04:00
Kconfig	arm: cortex_m: select by default FP sharing mode when using the FPU	2021-02-02 17:58:58 -05:00