Delete the native timer soft IP driver as we will be reusing the Altera's HAL drivers for most of the soft IP's. Add shim driver support for Altera timer system clock soft IP. Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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#include <altera_common.h>
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#include "altera_avalon_timer_regs.h"
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#include "altera_avalon_timer.h"
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static u32_t accumulated_cycle_count;
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static void timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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/* Clear the interrupt */
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alt_handle_irq((void *)TIMER_0_BASE, TIMER_0_IRQ);
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_sys_clock_tick_announce();
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}
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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IOWR_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE,
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sys_clock_hw_cycles_per_tick & 0xFFFF);
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IOWR_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE,
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(sys_clock_hw_cycles_per_tick >> 16) & 0xFFFF);
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IRQ_CONNECT(TIMER_0_IRQ, 0, timer_irq_handler, NULL, 0);
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irq_enable(TIMER_0_IRQ);
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alt_avalon_timer_sc_init((void *)TIMER_0_BASE, 0,
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TIMER_0_IRQ, sys_clock_hw_cycles_per_tick);
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return 0;
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}
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u32_t _timer_cycle_get_32(void)
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{
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/* RTOS-2676: Per the Altera Embedded IP Peripherals guide, you cannot
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* use a timer instance for both the system clock and timestamps
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* at the same time.
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*
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* Having this function return accumulated_cycle_count + get_snapshot()
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* does not work reliably. It's possible for the current countdown
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* to reset to the next interval before the timer interrupt is
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* delivered (and accumulated cycle count gets updated). The result
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* is an unlucky call to this function will appear to jump backward
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* in time.
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*
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* To properly obtain timestamps, the CPU must be configured with
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* a second timer peripheral instance that is configured to
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* count down from some large initial 64-bit value. This
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* is currently unimplemented.
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*/
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return accumulated_cycle_count;
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}
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