bba98a9c38
The earlier xtensa layer put the timer initialization and update directly into the interrupt handler, which is... weird. Under asm2, it's just a regular ISR and needs to do the work in the driver. Really, this driver needs a bunch of cleanup. The xtensa CPU timer is two registers and one ISR: a global cycle count register, and a compare register that will fire the IRQ when they match. There is *way* too much code here. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| .. | ||
| altera_avalon_timer_hal.c | ||
| arcv2_timer0.c | ||
| CMakeLists.txt | ||
| cortex_m_systick.c | ||
| hpet.c | ||
| Kconfig | ||
| loapic_timer.c | ||
| native_posix_timer.c | ||
| nrf_rtc_timer.c | ||
| pulpino_timer.c | ||
| riscv_machine_timer.c | ||
| sys_clock_init.c | ||
| xtensa_sys_timer.c | ||