zephyr/arch/xtensa/core
Daniel Leung 52993afd62 Revert "arch: xtensa: Use reset-vector.S in booloader code"
This reverts commit 9987c2e2f9
which spills SoC configs into architecture files and is not
exactly desirable. So revert it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-02-08 10:01:24 +02:00
..
offsets headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
startup Revert "arch: xtensa: Use reset-vector.S in booloader code" 2020-02-08 10:01:24 +02:00
atomic.S xtensa: fix atomic_cas reporting value swapped even when not 2020-01-08 19:57:05 -05:00
CMakeLists.txt arch: xtensa: Add support for Intel Apollolake 2020-02-05 10:43:25 -05:00
cpu_idle.c tracing: move headers under include/tracing 2020-02-07 15:58:05 -05:00
crt1.S headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
fatal.c xtensa: add support to build HAL as part of build process 2019-12-18 20:24:18 -05:00
irq_manage.c arch: xtensa: Add support for Intel Apollolake 2020-02-05 10:43:25 -05:00
irq_offload.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00
window_vectors.S headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
xtensa_intgen.py xtensa: xtensa_intgen.py: Change 'not lvl in ...' to 'lvl not in ...' 2019-09-07 07:55:01 -04:00
xtensa_intgen.tmpl
xtensa-asm2-util.S xtensa: remove legacy arch implementation 2019-09-12 01:26:34 -04:00
xtensa-asm2.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00