74ded5884f
RISC-V CLIC can trigger edge-triggered interrupts by software, but the available IRQ sources depend on the hardware implementation. Clarifies the IRQ source for GD32VF103 and adds support for AE350 CLIC. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com> |
||
|---|---|---|
| .. | ||
| cache | ||
| common | ||
| condvar/condvar_api | ||
| context | ||
| device | ||
| early_sleep | ||
| events | ||
| fatal | ||
| fifo | ||
| fpu_sharing | ||
| gen_isr_table | ||
| interrupt | ||
| ipi_cascade | ||
| ipi_optimize | ||
| lifo | ||
| mbox | ||
| mem_heap/k_heap_api | ||
| mem_protect | ||
| mem_slab | ||
| mp | ||
| msgq | ||
| mutex | ||
| obj_core | ||
| obj_tracking | ||
| pending | ||
| pipe | ||
| poll | ||
| profiling/profiling_api | ||
| queue | ||
| sched | ||
| semaphore | ||
| sleep | ||
| smp | ||
| smp_abort | ||
| smp_boot_delay | ||
| smp_suspend | ||
| spinlock | ||
| stack/stack | ||
| threads | ||
| tickless/tickless_concept | ||
| timer | ||
| usage/thread_runtime_stats | ||
| workq | ||
| xip | ||