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tests: kernel: gen_isr_table: add available IRQ number for AE350 CLIC

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RISC-V CLIC can trigger edge-triggered interrupts by software, but the
available IRQ sources depend on the hardware implementation.
Clarifies the IRQ source for GD32VF103 and adds support for AE350 CLIC.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2024-07-31 14:39:51 +08:00 committed by Anas Nashif
parent 24a1baeda3
commit 74ded5884f
1 changed files with 7 additions and 2 deletions
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9
tests/kernel/gen_isr_table/src/main.c
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@ -46,15 +46,20 @@ extern const uintptr_t _irq_vector_table[];
#error "Target not supported"
#endif
#elif defined(CONFIG_RISCV_HAS_CLIC)
#elif defined(CONFIG_SOC_GD32VF103)
#define ISR1_OFFSET 3
#define ISR3_OFFSET 17
#define ISR5_OFFSET 18
#define TRIG_CHECK_SIZE 19
#elif defined(CONFIG_SOC_ANDES_AE350_CLIC)
#define ISR1_OFFSET 19
#define ISR3_OFFSET 20
#define ISR5_OFFSET 21
#define TRIG_CHECK_SIZE 22
#else
#if !defined(IRQ1_USED)
/* RISC-V has very few IRQ lines which can be triggered from software */
/* RISC-V CLINT has very few IRQ lines which can be triggered from software */
#define ISR3_OFFSET 1
#endif